一种具有高线性度MOS采样开关的采样保持电路

通过采样保持电路中运放的复用,提出了一种具有高线性度MOS采样开关的模数转换器前端采样保持电路结构。这种结构可以显著降低采样开关导通电阻变化引入的非线性,从而在不增加开关面积和功耗的情况下,实现了高性能的采样保持电路。基于0.13?m的标准CMOS工艺,对提出的采样保持电路进行了仿真。在采样时钟频率为100MHz,输入信号频率1MHz时,仿真结果显示,无杂散动态范围(SFDR)达到了116.6dB,总谐波失真(THD)达到了112.7dB,信号谐波噪声比（SNDR）达到103.7dB,可以满足14比特流水线ADC对采样保持电路的要求。     

A new high-speed, high-resolution open-loop CMOS sample and hold

A new open loop, high resolution CMOS sample and hold (S/H) circuit is introduced in this article. This circuit is constructed based on a new method which leads to a great reduction in dependency of the storing charge of the holding capacitors to the charge injection of transistors. It is a combination of dummy switches and auxiliary capacitors in order to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it is reached to a great improvement in signal to noise and distortion ratio up to about 15 dB and it’s ENOB is equivalent with about 16 bits. Another advantages of our proposed design are it’s lower power dissipation and it’s high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the threshold voltage’s variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications.     

一种12位50MS/s CMOS流水线A/D转换器

采用TSMC 0.18μm 1P6M工艺设计了一个12位50 MS/s流水线A/D转换器（ADC）。为了减小失真和降低功耗,该ADC利用余量增益放大电路（MDAC）内建的采样保持功能,去掉了传统的前端采样保持电路;采用时间常数匹配技术,保证输入高频信号时,ADC依然能有较好的线性度;利用数字校正电路降低了ADC对比较器失调的敏感性。使用Cadence Spectre对电路进行仿真。结果表明,输入耐奎斯特频率的信号时,电路SNDR达到72.19 dB,SFDR达到88.23 dB。当输入频率为50 MHz的信号时,SFDR依然有80.51 dB。使用1.8 V电源电压供电,在50 MHz采样率下,ADC功耗为128 mW。     

适用于12 bit流水线ADC采样保持电路的设计

介绍了一种用于12 bit,20 MS/s流水线模数转换器前端的高性能采样/保持电路。该电路采用全差分结构、底极板采样来消除电荷注入和时钟馈通误差。采用栅压自举开关,并通过对电路中的开关进行组合优化,极大地提高了电路的线性性能。同时,运算放大器采用折叠式增益增强结构,以获得较高的增益和带宽。采用CSMC公司的0.5μm CMOS工艺库,对电路进行了仿真和流片。结果表明,在5 V电源电压下,采样频率为20 MHz,采样精度可达到0.012%,在输入信号为奈奎斯特频率时,无杂散动态范围(SFDR)为76 dB。     

用于12 bit 40 MS/s低功耗流水线ADC的采样保持电路

设计了一个可降低12 bit 40 MHz采样率流水线ADC功耗的采样保持电路。通过对运放的分时复用,使得一个电路模块既实现了采样保持功能,又实现了MDAC功能,达到了降低整个ADC功耗的目的。通过对传统栅压自举开关改进,减少了电路的非线性失真。通过优化辅助运放的带宽,使得高增益运放能够快速稳定。本设计在TSMC0.35μm mix signal 3.3 V工艺下实现,在40 MHz采样频率,输入信号为奈奎斯特频率时,其动态范围(SFDR)为85 dB,信噪比(SNDR)为72 dB,有效位数(ENOB)为11.6 bit,整个电路消耗的动态功耗为14 mW。     

A 12-bit 250 MS/s pipeline ADC with 78 dB SFDR in 0.13-µm CMOS

A 12-bit 250 MS/s pipeline ADC is presented and implemented in 0.13 µm CMOS process. To reduce the load capacitance of each pipeline stage and save area, the inter-metal capacitors are adopted as input sampling capacitors of the comparators. A fully integrated reference buffer associated with a simulation scheme is proposed to improve the settling speed and PSRR of the differential reference voltage. To reduce the overall power a low cost foreground calibration for capacitor mismatches is employed. The single-stage telescopic with gain-boosting amplifiers and an improved bias is applied in each stage due to its high power efficiency. Additionally, the timing in the sampling phase is optimised to achieve high sampling linearity. Even harmonics induced by parasitic capacitance are analysed profoundly and mitigated at the level of layout. The measured SNDR and SFDR are 63 and 78 dB with 38.1 MHz input, respectively, and remain 63 and 77 dB with Nyquist input. The ADC core area is 1.6 mm² and consumes 165 mW (reference buffer included, LVDS excluded) at 250 MS/s under 1.3 V.     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

一种12位2 GS/s BiCMOS采样保持电路

基于130 nm BiCMOS工艺,设计了一种12位高速采样保持电路,对电路的主要性能进行了分析。电路采用差分结构,采样开关是开环交换射极跟随开关。在输入信号范围内,缓冲器的线性度较高。采用Cadence Spectre软件进行仿真。结果表明,当采样率为2 GS/s,模拟输入差分信号为992 MHz频率、0.5V_pp幅度的正弦波时,SFDR达75.11 dB,SNDR达73.82 dB,电路功耗仅为98 mW,满足了12位采样保持的要求。     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converterin a 0.25-μm digital CMOS process

The design of a high-speed analog-to-digital (A/D) converter for hard disk drive read channels is described. The A/D converter uses a flash architecture with an interleaved sample and hold and interpolating comparator pre-amplifiers. It has 6 bits of resolution at full speed as well as a 7 bit mode operating at a lower speed. The 7 bit mode is useful for servo signal processing. This A/D converter has been implemented in a four-level metal single-poly 0.25 μm CMOS technology. The device operates at a speed of up to 700 MSamples/s in the 6 bit mode while maintaining a signal-to-noise-plus-distortion rate (SNDR) of greater than 35 dB at input frequencies of up to one-fourth the sampling rate. In the 7 bit mode, the device operates at up to 200 MSamples/s with a SNDR greater than 41 dB. It occupies an active area of 0.45 mm² and consumes less than 187 mW of power     

A 10 MS/s 11-bit 0.19 mm $^{2}$ Algorithmic ADC With Improved Clocking Scheme

A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19$~{hbox{mm}}^{2}$ is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13$~mu{hbox{m}}$ thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.      

Linearity improvement of source degenerated transconductance amplifiers

Mobility degradation is predominant in submicron CMOS technology. The effect of this mobility reduction in a linear operational transconductance amplifier (OTA) with signal attenuation and source degeneration is examined in this study. Theoretical analysis shows that the cubic non-linearity in the attenuator helps to improve the linearity of the source degenerated transconductor by partial cancellation of the harmonic distortion component. Such a linear transconductor and a third order low pass filter based on this linear OTA are fabricated in UMC 180 nm CMOS process technology. Experimental results show that third order intermodulation distortion of the linear OTA is less than ?60 dB for 500 mVpp differential input signal while for 2 % transconductance variation the linear range is about 1.2 Vpp. The linear transconductor consumes only 0.45 mW of power with 1.8 V supply.     

A 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dB SFDR

This paper describes a 10 or 12 bit programmable successive approximation register ADC for bridge stress monitoring systems requiring high-resolution, high linearity, low power and small size. Its sampling rate is scalable, from 0 to 200 kS/s. The proposed ADC employs a novel time-domain comparator with offset cancellation. Prototyped in a 0.18-μm, 6MIP CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 68.74 dB (11.13), an SFDR of 90.36 dB, while dissipating 579.6 μW from a 1.8-V supply. The on-chip calibration improves the DNL from +0.2/?0.74 LSB to +0.23/?0.25 LSB and INL from +1.27/?0.97 LSB to +0.41/?0.4 LSB.     

一种高性能CMOS采样/保持电路

提出了一种高性能CMOS采样/保持电路,它采用全差分电容翻转型的主体结构有效减小了噪声和功耗。在电路设计中提出了新型栅源电压恒定的自举开关来极大减小非线性失真,并同时有效抑止输入信号的直流偏移。该采样/保持电路采用0.18μm1P-6M CMOS双阱工艺来实现,在1.8V电源电压、32MHz采样速率下,输入信号直到奈奎斯特频率时仍能达到86.88dB的无杂散动态范围(SFDR),电路的信号噪声失真比(SNDR)为73.50dB。最后进行了电路的版图编辑,并对样片进行了初步测试,测试波形表明,电路实现了采样保持的功能。     

1.8Vpp 250MS/s低谐波失真流水线ADC

采用40nm CMOS工艺设计了一款在250MS/s采样率下具有1.8Vpp满摆幅和低谐波失真性能的流水线ADC（Analog-to-Digital Converter）.针对传统源跟随器结构的输入缓冲器在大摆幅下驱动大采样电容时线性度恶化的问题,采用了改进型电流注入技术和漏端电压自举技术.ADC中实现采样和电荷转移功能的开关采用薄栅器件设计,其工作电压由片上LDO（Low Dropout Regulator）提供,在降低开关寄生和电荷注入的同时保障了器件的可靠性.测试结果表明,对于10.1MHz单音输入,该ADC在-1dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别为68.3dB、76.4dBc、-75.1dBc,在-1.57dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别达68.3dB、80.1dBc、-78.6dBc.     

A 10-b, 100-MS/s CMOS A/D converter

A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-μm CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same     

一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is ±1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR     

A 12-bit 100 MS/s pipelined SAR ADC with addition-only digital error correction

A new redundant successive approximation register (SAR) ADC architecture with digital error correction is presented to avoid the comparator offset issue and subtraction operations. A 2-channel 12-bit 100 MS/s SAR ADCs based on the proposed architecture with voltage-controlled delay lines based time-domain comparator is designed in a 65 nm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.81 dB (11.47 ENOB), a spurious free dynamic range (SFDR) of 80.33 dB for a near Nyquist input at 100 MS/s, while dissipating 11 mW from a 1.2-V supply, giving a FOM of 38.8 fJ/Conversion-step.