Two-stage fuzzy inference system for symbolic simplification of analog circuits

This paper presents a knowledge-based fuzzy approach to symbolic circuit simplification in an effort to imitate human reasoning and knowledge of circuit designer experts. The fuzzy approach differs from the conventional simplification techniques in that it can efficiently combine different input variables to obtain optimal simplified expressions. Additionally, this method was chosen due to its adjustability and interpretability, as well as its ability to manage very complex symbolic expressions. The proposed algorithm uses fuzzy logic to simplify the symbolic circuit transfer functions in two stages. In the first stage, a fuzzy system is applied to directly eliminate nonessential circuit components, resulting simplified circuit topology which also yields simpler transfer function. In the second stage, another fuzzy system is used to further simplify the symbolic transfer function from the already simplified circuit, such that deeper insight into the circuit behavior can be obtained. Symbolic and numerical results show that the fuzzy approach outperforms the conventional techniques in terms of accuracy, expression complexity, and CPU running time.     

ISAAC: a symbolic simulator for analog integrated circuits

The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The program's capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm     

Efficient symbolic computation of approximated small-signalcharacteristics of analog integrated circuits

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics of large analog integrated circuits. The expressions are approximated while they are computed, so that only those terms are generated which remain in the final expression. This principle causes drastic savings in CPU time and memory, compared with previous symbolic analysis tools. In this way, the maximum size of circuits that can be analyzed, is largely increased. By taking into account a range for the value of a circuit parameter rather than one single number, the generated expressions are also more generally valid. Mismatch handling is explicitly taken into account in the algorithm. The capabilities of the new tool are illustrated with several experimental results     

A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Applying symbolic techniques for analog circuit analysis is a traditional research subject, which has lasted for over half a century. The past decade has witnessed a significant advancement of the symbolic techniques developed specifically for large analog integrated circuits. The key methodology introduced is a data structure called binary decision diagram (BDD) which was established originally for logic design and verification. The application of the BDD technique for analog circuit analysis has the following features: (1) It is a compact data structure so that data redundancy in symbolic analysis can be eliminated. (2) It provides a mechanism for implicit enumeration method so that exhaustive enumeration commonly performed in symbolic analysis can be avoided. (3) Numerical evaluation on a BDD can be made extremely efficient, making it an excellent means for repetitive analysis. More advanced features are yet to be explored. This survey brings together the significant research results published in the past decade and provides a tutorial overview on the basic principles of applying BDD to analog circuit analysis. Some new directions that are potentially valuable for developing future analog design automation tools are discussed and a design example is given to illustrate the application of symbolic techniques.     

Interactive AC modeling and characterization of analog circuits via symbolic analysis

An advanced symbolic analyzer, called ASAP, has been developed for the automatic ac modeling of analog integrated circuits. ASAP works on a data base of model primitives and provides error-free symbolic expressions for the different system functions of analog circuits composed by the primitives. Both complete and simplified expressions can be calculated. Two simplification criteria have been implemented. The basic one is based on pruning the least significant terms in the different system function coefficients. This may yield important errors in pole and zero locations. To avoid that, an improved criterion has been developed where pole and zero displacements are forced to remain bounded. Also implemented are routines for symbolic pole/zero extraction and parametric ac circuit characterization. ASAP uses the signal flow graph method for symbolic analysis and has been written in the C language for portability. Together with portability, efficiency and ability to manage complexity have been fundamental goals in the implementation of ASAP. These features are demonstrated in this paper via practical examples.     

CMOS analog integrated circuits based on weak inversion operations

A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.     

改进符号化模拟电路仿真器的启发式符号排序

基于二分决策图(BDD)的符号化仿真器性能很大程度上依赖于符号排序.现对一个基于拓扑的符号化模拟电路仿真器的符号排序进行了研究,提出了一种根据电路功能模块对符号排序的启发式排序方法.测试表明该启发式符号排序方法明显比随机排序仿真具有更快仿真速度.     

Potential of MOS technologies for analog integrated circuits

Reviews the rapid progress in MOS analog circuit techniques over the past three years, and attempts to estimate the near-term attainable characteristics of MOS LSI circuits which incorporate both analog and digital functions.     

MOSFET thermal noise modeling for analog integrated circuits

The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements     

模拟集成电路模块版图的生成系统

介绍了模拟集成电路模块版图的开发系统.系统用高效的过程化版图描述语言构造模拟模块,编译产生与工艺及应用无关的模块版图生成器.系统的网络识别和模块内布线功能自动完成模块网络的完全连通,基于优选的电气特性驱动版图生成,提高设计可靠性.该系统已辅助设计出多个高性能集成运算放大器、模拟开关等芯片版图.     

A performance-driven placement tool for analog integrated circuits

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples     

Design principles for low-voltage low-power analog integrated circuits

In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.     

基于分数阶相关的模拟集成电路软故障诊断* Deng Yong(邓勇), Shi Yibing(师奕兵)and Zhang Wei(张伟)

针对模拟集成电路软故障诊断的难题,提出了基于分数阶相关的方法。首先,利用分数阶小波包将待测试电路(CUT)的Volterra级数进行分解,计算出分数阶相关函数。然后,用得到的分数阶相关函数构造出待测试电路的故障特征。通过对故障特征的比较,可以将待测试电路的各种软故障状态进行辨识并对故障实现定位。标准电路的仿真实验描述了这一方法并验证了该方法对模拟集成电路软故障诊断的有效性。     

Power estimation methods for analog circuits for architecturalexploration of integrated systems

This paper describes methods for analog-power estimation and applies them practically to two different classes of analog circuits. Such power estimators, which return a power estimate given only a block's specification values without knowing its detailed circuit implementation, are valuable components for architectural exploration tools and hence interesting for high-level system designers. As an illustration, two estimators are presented: one for high-speed analog-to-digital converters (ADCs) and one for analog-continuous time filters. The ADC power estimator is a technology scalable closed formula and yields first-order results within an accuracy factor of about 2.2 for the whole class of high-speed Nyquist-rate ADCs. The filter-power estimator is of a more complex nature. It uses a crude filter synthesis, in combination with operational transconductor amplifier behavioral models to generate accurate results as well, but restricted to certain filter implementations     

Hierarchical yield estimation of large analog integrated circuits

A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.