A pipeline A/D converter architecture with low DNL

A pipeline analog-to-digital converter architecture can reduce the differential nonlinearity (DNL) with a swapping technique without involving special calibration techniques. An implementation of the overrange stages in the analog pipeline suitable for high-speed applications is proposed. A 14-bit 5-MSample/s converter has been fabricated in a double-poly 0.5-μm CMOS process. The 3.3×3.3 mm ² chip dissipates 320 mW from a single 5 V supply and achieves a signal-to-noise ratio of 79 dB, a dynamic range of 82 dB, and a DNL below 0.4 LSB     

A new successive approximation architecture for low-power low-cost CMOS A/D converter

A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm/sup 2/ with the TSMC 0.35-/spl mu/m single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.     

PCM telephony: reduced architecture for a D/A converter and filtercombination

Large dynamic range and high power-supply rejection ratio (PSRR) are achieved in a pulse-code-modulation (PCM) decoder by using differential circuit techniques and by reducing the number of operational amplifiers on the interpolation filter to four (including the output buffer). This reduction is achieved by: (1) exploiting the sin x/x distortion and using a simple integrating configuration in the digital-to-analog converter; and (2) properly manipulating the signal flowgraph of the filter     

A/D和D/A转换器IC

代码转换器提高DSP效率 TLV320AIC10 16位代码转换器提供连续数据传输,可支持DSP自动缓冲单元,减少因缓冲(最高达64kB)不足而引起的中断。该器件特性有每秒22k的采样速率,一个串行接口,增益范围为-36～24dB的可编程增益放大器,一个2:1模拟多路复用器,以及节能备用模式。其它性能包括:工作电压3～5.5V,在采样速率为每秒8k时功耗为39mW。     

Current-mode A/D converter

The authors report the design of a new current-mode A/D converter, based on a modified successive-approximations model, in 1.2 μm CMOS technology. The proposed circuit is characterised by good accuracy and fast dynamic performance, low power consumption and small occupation area. SPICE simulations allow the design approach to be validated and the electrical performance of the ADC to be predicted     

了解D/A转换器的架构--架构与制造工世决定D/A 转换器的性能

数模转换器(D/A)在许多应用中起着重要的作用.了解常用D/A架构及相关的权衡折衷方法,将有助于您针对某项具体应用选择最为合适的D/A.     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

A superconducting tracking A/D converter

The design and fabrication of a superconducting A/D converter using Josephson technology are described. The 4-b A/D converter circuit was fabricated using a ten-level all-Nb technology. It uses a self-aligned lift-off process to define the Nb-Al₂O₃ -Nb Josephson junctions. Results from experiments performed on the prototype system at a few kilohertz sampling rate are presented     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

A power-adaptable A/D converter with integrated data compression

A novel adaptable analog/digital converter (ADC) that combines analog/digital conversion and entropy-coding for integrated data compression and low-power operation is reported. The converter has high flexibility of operation in terms of adaptable resolution, conversion rate and input signal statistics. This feature allows to adaptively react to changes of the situation and to put the device in each case into the optimum configuration. The ADC has been realized in a 0.6 μm CMOS technology with a peak resolution of 12 bit and 200 kS/s maximum sampling rate. A comprehensive power model of the converter is presented that reflects precisely the power consumption determined from experiments. The model is very useful for optimizing the converter configuration in the node of a wireless sensor network for specific situations. A feasible real-life application is demonstrated.     

A new AC/AC multilevel converter family

A new ac/ac modular multilevel converter (M/sup 2/LC) family will be introduced. The new concept stands out due to its modularity and superior control characteristics. The stringent modularity results in a very cost-efficient and versatile converter construction. This new M/sup 2/LC concept is well suited to a wide range of multiphase ac/ac converters. The basic working principle together with the static and dynamic behavior are explained in detail on a single-phase ac/ac converter enabling four-quadrant operation. It is demonstrated that this converter concept fulfils the demanding requirements for future ac-fed traction vehicles very well.     

A high-speed 7 bit A/D converter

A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4/spl times/2.5 mm.     

A monolithic 14-bit D/A converter

A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described. Over a temperature range from -50/spl deg/ to 70/spl deg/C the nonlinearity is less than one-half least significant bit (/SUP 1///SUB 2/LSB). Dynamic tests show a distortion at a level of about -90 dB with respect to the maximum sinewave output. Nearly no glitches are found, so the converter can be operated without a deglitcher circuit. The chip, with a size of 3.1/spl times/3.2 mm, contains all elements needed, except the output amplifier and digital input latches.     

高速A/D转换器的选择--在选择A/D变换器时,其应用场合是一条重要的依据

模数转换器是连接模拟和数字世界的一个重要接口.A/D转换器将现实世界的模拟信号变换成数字位流以进行处理、传输及其他操作.     

5 GHz Josephson A/D converter

A four-bit A/D convertor using Nb/AlO_x/Nb Josephson junctions was fabricated. The circuit was designed to preserve the matching of characteristic impedances at all nodes. Four-bit A/D conversion was confirmed at a low frequency. The A/D convertor correctly operated at up to 5 GHz for two-bit conversion