Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.     

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices,n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications.In this paper,backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs.The thickness of a drift layer was 120 μm,which was designed for a blocking voltage of 13 kV.The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V,with a differential specific on-resistance of 140 mΩ·cm2.     

Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics

We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd₂O₃) from a silicon oxide (SiO₂) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).     

Investigation of the Electrical and Thermal Performance of SOI MOSFETs with Modified Channel Engineering

In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature.     

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect

In this paper, we propose a unique feature exhibited by novel nanoscale metal oxide semiconductor field effect transistors (MOSFETs) with an undoped buried region (UBR) under the channel and a buried oxide only under the source and drain region. The key idea in this work is suppression of the self-heating effect and gate–substrate capacitance improvement by modifying the buried layer. As a result, we demonstrate that the proposed structure called undoped buried region MOSFET (UBR-MOSFET) exhibits gate–substrate improvement in addition to excellent temperature performance when compared to conventional structures. Using two-dimensional and two-carrier device simulation, we have examined various design issues of the UBR-MOSFET and provided the reasons for the improved performance. The simulated results show that the novel structure is a suitable device for high temperature and electrical performances.     

Carrier Type Control of WSe2 Field‐Effect Transistors by Thickness Modulation and MoO3 Layer Doping

Control of the carrier type in 2D materials is critical for realizing complementary logic computation. Carrier type control in WSe₂ field‐effect transistors (FETs) is presented via thickness engineering and solid‐state oxide doping, which are compatible with state‐of‐the‐art integrated circuit (IC) processing. It is found that the carrier type of WSe₂ FETs evolves with its thickness, namely, p‐type (<4 nm), ambipolar (≈6 nm), and n‐type (>15 nm). This layer‐dependent carrier type can be understood as a result of drastic change of the band edge of WSe₂ as a function of the thickness and their band offsets to the metal contacts. The strong carrier type tuning by solid‐state oxide doping is also demonstrated, in which ambipolar characteristics of WSe₂ FETs are converted into pure p‐type, and the field‐effect hole mobility is enhanced by two orders of magnitude. The studies not only provide IC‐compatible processing method to control the carrier type in 2D semiconductor, but also enable to build functional devices, such as, a tunable diode formed with an asymmetrical‐thick WSe₂ flake for fast photodetectors.     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

Improvement of threshold voltage deviation in damascene metal gatetransistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (ΔV _th) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, ΔV_th of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (ΔV_th) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta₂O₅ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN     

SiC电力电子器件研究现状及新进展

由于硅材料本身的限制,传统硅电力电子器件性能已经接近其极限,碳化硅(SiC)器件的高功率、高效率、耐高温、抗辐照等优势逐渐突显,成为电力电子器件一个新的发展方向.综述了SiC材料、SiC电力电子器件、SiC模块及关键工艺的研究现状,重点从材料、器件结构、制备工艺等方面阐述了SiC二极管、金属氧化物半导体场效应晶体管(MOSFET)、结晶型场效应晶体管(JFET)、双极结型晶体管(BJT)、绝缘栅双极晶体管(IGBT)及模块的研究进展.概述了SiC材料、SiC电力电子器件及模块的商品化情况,最后对SiC材料及器件的发展趋势进行了展望.     

On the Spatial Localization of Free Electrons in 4<Emphasis Type="Italic">H</Emphasis>-SiC MOSFETS with an <Emphasis Type="Italic">n</Emphasis> Channel

The problem of the spatial localization of free electrons in 4H-SiC metal—oxide—semiconductor field effect transistors (MOSFETS) with an accumulation- and inversion-type n channel is theoretically analyzed. The analysis demonstrates that, in optimally designed accumulation transistors (ACCUFETs), the average distance from the surface, at which free electrons are localized, may be an order of magnitude larger than that in inversion MOSFETs. This can make 4H-SiC ACCUFETs advantageous as regards the effective carrier mobility in a conducting channel.     

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (~350 cm²/V-s) in the depletion regime into accumulation (~200 cm²/V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (~27 cm²/V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime     

Impact of Thickness on Contact Issues for Pinning Effect in Black Phosphorus Field‐Effect Transistors

Metal/semiconductor contact is a significant constraint in short‐channel field effect transistors (FETs) comprising black phosphorus (BP) and other 2D semiconductors. Due to the pinning effect at metal/2D semiconductor interface, the Schottky barrier usually does not follow the Schottky–Mott rule, resulting in thickness‐dependent FET performance. In this work, the Schottky barrier in BP FETs is investigated via theory calculation and electrical measurement. A simple metal/BP contact model is presented based upon thickness‐dependent electrical characteristics of BP FETs. The model considers the Schottky barrier as a combined effect of the Schottky–Mott rule and the pinning effect and provides a feasibility to track the conducting behavior of other 2D semiconductor FETs.     

Extraction of Substrate Resistance in Bulk FinFETs Through RF Modeling

A new method to extract substrate resistance (R_sub) for small-sized nano-scale metal oxide semiconductor field effect transistors (MOSFETs) including bulk FinFETs is proposed and compared with conventional method. The R_sub's extracted from small-size MOSFETs by using the proposed method are shown to have frequency independent characteristics, unlike those from the conventional method. Proposed equivalent circuit explains well the R_sub behavior with body width. The proposed model showed very good agreement (error in Y₂₂~3%) with three-dimensional device simulation     

nanoMOS 2.5: A two-dimensional simulator for quantum transport in double-gate MOSFETs

A program to numerically simulate quantum transport in double gate metal oxide semiconductor field effect transistors (MOSFETs) is described. The program uses a Green's function approach and a simple treatment of scattering based on the idea of so-called Buttiker probes. The double gate device geometry permits an efficient mode space approach that dramatically lowers the computational burden and permits use as a design tool. Also implemented for comparison are a ballistic solution of the Boltzmann transport equation and the drift-diffusion approaches. The program is described and some examples of the use of nanoMOS for 10 nm double gate MOSFETs are presented.     

Extraction of substrate parameters for RF MOSFETs based on four-port measurement

In this work, a new method for extracting substrate parameters of radio frequency (RF) metal oxide semiconductor field effect transistors (MOSFETs) based on four-port measurement is presented. A T-liked substrate resistance network is used and the values of all components in the cold MOSFETs were extracted directly from the four-port data between 250 MHz and 8.5 GHz. The output admittance Y/sub 22/ can be well modeled up to 26.5 GHz based on the extracted substrate resistances and the other extrinsic capacitances extracted from an active device.     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

Investigation of temperature-dependent small-signal performances of TB SOI MOSFETs

This paper investigated the temperature dependence of the cryogenic small-signal ac performances of multi-finger partially depleted (PD) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs), with T-gate body contact (TB) structure. The measurement results show that the cut-off frequency increases from 78 GHz at 300 K to 120 GHz at 77 K and the maximum oscillation frequency increases from 54 GHz at 300 K to 80 GHz at 77 K, and these are mainly due to the effect of negative temperature dependence of threshold voltage and transconductance. By using a simple equivalent circuit model, the temperature-dependent small-signal parameters are discussed in detail. The understanding of cryogenic small-signal performance is beneficial to develop the PD SOI MOSFETs integrated circuits for ultra-low temperature applications.     

Synchrotron x-ray irradiation effects on the device characteristics and the resistance to hot-carrier damage of MOSFETs with 4 nm thick gate oxides

The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs, device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6000 mJ/cm².     

An analysis and experimental approach to MOS controlled diodesbehavior

The metal oxide semiconductor (MOS)-controlled diode (MCD) is a new class of power semiconductor diode that can achieve ideal diode performance. In this paper, experimental verification of the MCD key concept is presented for the first time by using commercially available power metal oxide semiconductor field effect transistors (MOSFETs) operating as MCDs. Measurements of the reverse recovery currents and reverse recovery charges of these “MCDs” are obtained and compared with the body diodes of the MOSFETs. These measurements suggest that MCDs can reduce the reverse recovery current, storage charge, and switching loss significantly. Optimized MCD performances at 1.2 kV, 2.4 kV, and 4.5 kV are also predicted based on numerical simulations. Ideal performance of the MCD close to that predicted by the device simulation should be obtained once an optimized MCD is developed