Low power CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.     

用于神经记录的低功耗CMOS前置放大器

本文提出了一种应用于胞外神经记录的全差分带通CMOS前置放大器。这种放大器采用“容性耦合结合容性反馈”式拓扑结构。放大器具有20.4 dB的中带增益,且无直流增益。高频-3 dB截止频率为6.7 KHz,而低频-3 dB截止频率可根据不同频段场电位或动作电位的放大需求作出调整。在3.3 V供电下,放大器的通带设置为0.15 Hz到6.7 KHz（可同时记录本地场电位和神经元峰电位）,测得输入参考噪声为8.2 μVrms,功耗仅为23.1 μW。文中也设计了为前置放大器提供偏置电压和偏置电流的带隙参考电路。该原型芯片基于0.35-μm N阱CMOS 2P4M工艺设计与制造,包括前置放大器和偏置电路在内,有源区面积为0.22 mm2。     

一种极低功耗的CMOS带隙基准源

随着SoC在便携产品中应用的迅猛发展,低功耗技术变得越来越重要。本文采用了0.18um的标准CMOS工艺来,设计了一种无电阻、工作在亚阈值区的低功耗、小面积的CMOS电压基准源。这个带隙基准可以灵活运用于极低功耗的SoC系统中。这个电路的电源电流大约为150nA,可以在1.5V～3.3V之间的电源电压下工作,基准源的输出电压的线性度为44.4ppm/V。当电源电压为1.5V,室温下带隙基准电路的输出电压为1.1126V,100Hz频率下的电源抑制比为-66dB,当温度在-20℃与80℃之间变化时,输出电压的温度系数是55ppm/℃。整个带隙基准的芯片面积是0.011mm2。     

Quantum transport simulation of the two-dimensional GaSb transistors

Owing to the high carrier mobility,two-dimensional (2D) gallium antimonite (GaSb) is a promising channel material for field-effect transistors (FETs) in the post-silicon era.We investigated the ballistic performance of the 2D GaSb metal-oxide-semiconductor FETs with a 10 nm-gate-length by the ab initio quantum transport simulation.Because of the wider bandgap and better gate-control ability,the performance of the 10-nm monolayer (ML) GaSb FETs is generally superior to the bilayer counterparts,including the three-to-four orders of magnitude larger on-current.Via hydrogenation,the delay-time and power consumption can be further enhanced with magnitude up to 35％ and 57％,respectively,thanks to the expan-ded bandgap.The 10-nm ML GaSb FETs can almost meet the International Technology Roadmap for Semiconductors (ITRS) for high-performance demands in terms of the on-state current,intrinsic delay time,and power-delay product.     

航天器低功耗电源控制器测控单元设计

本文针对航天器电源控制器智能化、低功耗等方面的设计需求,对电源控制器遥测遥控接口单元采用智能化控制设计,依托微处理器内部软件来执行电源系统全任务周期的控制和管理,提高电源系统的效率、可靠性、自主管理能力,并降低系统的静态功耗.     

NoC功耗与性能的研究

在当前高性能片上网络设计中,功耗和延迟是设计所面临的核心问题之一。在此着重阐述了构成低功耗和低延迟NoC的4种结构:低摆幅的信号传输结构、可重构的NoC结构、3D的IC设计结构、基于数据压缩机制的结构。通过对其功过原理的分析,比较了4种结构的优缺点,最后对未来低功耗、低延迟的NoC发展方向做出了预测。     

基于恒流二极管（CRD）的运算放大器低功耗研究

基于CRD对741双极型通用集成运放进行改进研究,通过CRD替代双极型集成运算放大器（OPAMP）输入级及偏置电路中做为恒流源的双极型器件,并利用Multisim 10和Cadence进行设计与仿真。结果表明,当电源电压改变时,双极型运算放大器输入级电流在0．290 mA到0．433 mA变化,而基于CRD的差分输入级电流恒定在0．239 mA到0．244 mA之间,且电流变化只有0．005 mA。当电源电压恒定在13 V时,双极型运算放大器偏置电流达到0．739 mA,而基于CRD偏置电路电流只有0．222 m。由此可知,基于CRD的运算放大器能实现更低功耗。     

测量大功率LDMOS晶体管特性的TRL校准方法研究

The impedance and output power measurements of LDMOS transistors are always a problem due to their low impedance and lead widths.An improved thru-reflect-line(TRL) calibration algorithm for measuring the characteristics of L-band high power LDMOS transistors is presented.According to the TRL algorithm,the individual two-port S parameters of each fixture half can be obtained.By de-embedding these S parameters of the test fixture,an accurate calibration can be made.The improved TRL calibration algorithm is successfully utilized to measure the characteristics of an L-band LDMOS transistor with a 90 mm gate width.The impedance of the transistor is obtained,and output power at 1 dB compression point can reach as much as 109.4 W at 1.2 GHz, achieving 1.2 W/mm power density.From the results,it is seen that the presented TRL calibration algorithm works well.     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

基于Atmega8低功耗智能微波探测器的设计

微波具有直线传播、波段宽、设备小、穿透力和抗干扰能力强等优点,基于此设计了一种基于Atmega8低功耗智能微波探测器,经测试,该探测器灵敏度高、功耗低、稳定性好,适用于自动门控制开关、室内外安全防范系统、ATM自动提款机的自动录像控制系统、野外安全警示等场所。     

一种低功耗K频段低噪声放大器

基于0.13μm锗硅(SiGe)双极型互补金属氧化物(Bipolar Complementary Metal Oxide Semi-conductor,BiCMOS)工艺,设计制作了一种高增益低功耗K频段低噪声放大器(Low Noise Amplifier,LNA),通过优化晶体管尺寸及利用硅通孔设计高品质因数射极退化...     

Low voltage copper phthalocyanine organic thin film transistors with a polymer layer as the gate insulator

Low voltage organic thin film transistors(OTFTs) were created using polymethyl-methacrylate-co g-lyciclyl-methacrylate(PMMA-GMA) as the gate dielectric.The OTFTs performed acceptably at supply voltages of about 10 V.From a densely packed copolymer brush,a leakage current as low as 2×10~(-8) A/cm~2 was obtained.From the measured capacitance-insulator frequency characteristics,a dielectric constant in the range 3.9-5.0 was obtained. By controlling the thickness of the gate dielectric,the threshold voltage ...     

基于聚合物绝缘栅的低电压有机薄膜晶体管

利用甲基丙烯酸甲酯-甲基丙烯酸环氧丙脂为栅绝缘层制备了酞箐铜有机薄膜晶体管,在电压为10V时器件具有较好的性能,栅绝缘层的漏电流密度低至2×10-8A/cm2 。测量其电容特性,该绝缘薄膜的介电常数介于3.9-5.0 。通过对绝缘层的减薄,阈值电压由 -3.5V 升至-2.0V,该酞箐铜有机薄膜晶体管可以在低电压下工作,其场效应迁移率为1.2×10-3 cm2/Vs 。     

水情自动测报系统遥测站低功耗设计研究

针对水情自动测报系统运行环境和特点,分析了影响遥测站功耗的主要因素,详细阐述了器件选型、电源控制、远程通信、软件编程等关键环节进行低功耗设计的策略与实现方法。据此设计的数据采集器在现场得到广泛运用,验证了本方法的有效性和实用性。     

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.     

基于ARM的低功耗语音增强系统设计

谱减法作为一种很有效的语音信号处理手段,广泛应用于现代语音增强系统中。针对低功耗设计的要求,本系统采用功耗低且功能强大的ARM芯片,用C语言编程将算法成功移植到ARM系统中,该系统功耗低,并有效地减小了噪声,改善了语音通信质量,有较好的实用性     

压控振荡器相位噪声、功耗和频率调谐特性的设计优化

To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise, power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and up-conversion of flicker noise from cross-coupled pair are reduced by improved self-switched biasing technology, leading to low close-in phase noise. Low power is achieved by low supply voltage and triode region biasing. To linearly tune the frequency and get constant gain, distributed varactor structure is adopted. The proposed VCO is fabricated in SMIC 0.18-μm CMOS process. The measured linear tuning range is from 2.38 to 2.61 GHz. The oscillator exhibits low phase noise of -77.5 dBc/Hz and -122.8 dBc/Hz at 10 kHz and 1 MHz offset, respectively, at 2.55 GHz oscillation frequency while dissipating 2.7 mA from 1.2 V supply voltage, which well meet design specifications.     

应用于2.4GHz无线传感网的超低功耗射频接收前端设计

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.     

智能涡街流量积算仪的超低功耗设计

通过对现有流量计及单片机在流量检测仪表中的应用现状的分析,结合流量计的发展趋势,设计了一种先进的智能涡街流量计,它能现场显示测试结果（包括瞬时流量、累计流量、温度、压力）,监测电池剩余容量,并且通过串口可与上位机通讯,实现自动抄表功能。整个系统采用超低功耗设计,单电源锂电池供电,使电池使用寿命延长至一年以上。     

低静态电流CMOS电压基准源设计

为了实现低功耗,尤其是低的静态功耗,在传统的带隙基准基础上设计的低静态电流CMOS基准源,是利用CMOS晶体管工作在弱反型区饱和漏电流随电压呈指数关系的原理实现的.在保证低温度系数18.9×10-6℃和高精度的同时,实现了低的静态电流.仿真的结果显示其输出基准电压是1.109 V,工作电压3 V时,消耗功耗为1.2 μW.