A peeling algorithm for extraction of the HBT small-signal equivalent circuit

Direct extraction is the most accurate method for the determination of equivalent-circuits of heterojunction bipolar transistors (HBTs). The method is based on first determining the parasitic elements and then the intrinsic elements analytically. The accuracy and robustness of the whole algorithm therefore is determined by the quality of the extraction of the extrinsic elements. This paper focuses on a new extraction method for the extrinsic capacitances which have proven to be the main source of uncertainty compared to the other extrinsic parameters. Concerning the intrinsic parameters, all the elements are extracted using exact closed-form equations, including exact expressions for the base-collector capacitances, which model the distributed nature of the base. The expressions for the base-collector capacitances are valid for both the hybrid-/spl pi/ and the physics-based T-topology equivalent circuits. Extraction results for InP HBT devices on measured S-parameters up to 100 GHz demonstrate good modeling accuracy.     

一种改进的用于SiGe HBT的焊盘模型参数提取技术

提出了一种适用于Si基器件的焊盘寄生参数的提取方法,并将此方法提取的焊盘寄生参数结果与用近似法提取的焊盘寄生参数结果的精度作了比较。比较结果表明,文中提出的线性拟合法精度较高。焊盘寄生参数提取并剥离后,对AMS 0.35μm BiCMOS工艺加工的SiGe HBT的小信号等效电路进行参数提取,其中,外部电阻用基极"过驱动电流"法提取,本征参数用分析法提取,将参数提取结果代入模型进行仿真,仿真得到的S参数在整个测试频率范围内均与测试结果吻合良好。     

A new small-signal modeling approach applied to GaN devices

A new small-signal modeling approach applied to GaN-based devices is presented. In this approach, a new method for extracting the parasitic elements of the GaN device is developed. This method is based on two steps, which are: 1) using cold S-parameter measurements, high-quality starting values for the extrinsic parameters that would place the extraction close to the global minimum of the objective function for the distributed equivalent circuit model are generated and 2) the optimal model parameter values are searched through optimization using the starting values already obtained. The bias-dependent intrinsic parameter extraction procedure is improved for optimal extraction. The validity of the developed modeling approach and the proposed small-signal model is verified by comparing the simulated wide-band small-signal S-parameter, over a wide bias range, with measured data of a 0.5-/spl mu/m GaN high electron-mobility transistor with a 2/spl times/50 /spl mu/m gatewidth.     

An Approach for Extracting Small-Signal Equivalent Circuit of Double Heterojunction δ-Doped PHEMTs for Millimeter Wave Applications

Pseudomorphic high electron mobility transistors (PHEMTs) are very important in millimeterwave application. A simple and accurate method for extracting small-signal equivalent curcuit for Double Heterojunction δ-doped PHEMT valid up to 40GHz is presented. First, the parasitic parameters of the equivalent circuit are determined using pinch off PHEMT except for PAD capacitances. The initial intrinsic elements are then determined by conventional analytical method. Advanced Design System is then used to optimize the whole model parameters with very small dispersion of initial values. Good agreement is obtained between simulation results and measured results for a 0.25um DH PHEMT.     

RF HBT oscillators with low-phase noise and high-power performance utilizing a (/spl lambda//4/spl plusmn//spl delta/) open-stubs resonator

This paper presents a new type of transmission-line resonator and its application to RF (microwave and millimeter-wave) heterojunction bipolar transistor (HBT) oscillators. The resonator is a parallel combination of two open stubs having length of /spl lambda//4/spl plusmn//spl delta/(/spl delta//spl Lt//spl lambda/), where /spl lambda/ is a wavelength at a resonant frequency. The most important feature of this resonator is that the coupling coefficient (/spl beta//sub C/) can be controlled by changing /spl delta/ while maintaining unloaded Q-factor (Q/sub u/) constant. Choosing a small value of /spl delta/ allows us to reduce /spl beta//sub C/ or equivalently to increase loaded Q-factor (Q/sub L/). Since coupling elements such as capacitors or electromagnetic gaps are not needed, /spl beta//sub C/ and Q/sub L/ can be precisely controlled based on mature lithography technology. This feature of the resonator proves useful in reducing phase noise and also in enhancing output power of microwave oscillators. The proposed resonator is applied to 18-GHz and 38-GHz HBT oscillators, leading to the phase noise of -96-dBc/Hz at 100-kHz offset with 10.3-dBm output power (18-GHz oscillator) and -104-dBc/Hz at 1-MHz offset with 11.9 dBm (38-GHz oscillator). These performances are comparable to or better than state-of-the-art values for GaAs- or InP-based planar-circuit fundamental-frequency oscillators at the same frequency bands.     

Small-signal modeling of HBTs using a hybridoptimization/statistical technique

A new formulation for extracting the elements of the small-signal equivalent-circuit model of heterojunction bipolar transistors (HBTs) is proposed in this paper. This approach avoids the main problem of the conventional extraction methods which, in most cases, is the use of brute-force optimization techniques to extract a large number of parameters. At the beginning, this technique first uses the extraction procedure of a low-frequency HBT model. An analytical formulation that allows the reduction of the number of the unknowns of the low-frequency model to only two, which have to be calculated using a suitable optimization technique, is described. This makes the optimization problem much easier to handle and increases the probability for converging to the actual elements of the model, thus avoiding the converging to spurious solutions. Secondly, in order to extend the model to higher frequencies, a statistical approach is proposed to extract parasitic extrinsic elements. An experimental validation is carried out on three HBT devices and satisfactory results are obtained up to 30 GHz     

A physical, yet simple, small-signal equivalent circuit for theheterojunction bipolar transistor

A physical, yet simple, small-signal equivalent circuit for the heterojunction bipolar transistor (HBT) is proposed. This circuit was established by analyzing in detail the physical operation of the HBT. The model verification was carried out by comparison of the measured and simulated S- and Z-parameters for both passive (reverse-biased) and active bias conditions. A feature of this model is that it uses a direct extraction method to determine the parasitic elements, in particular, the parasitic capacitances. The excellent agreement between the measured and simulated parameters was verified all over the frequency range from 0.25 to 75 GHz     

DC to high-frequency HBT-model parameter evaluation using impedanceblock conditioned optimization

A new heterojunction bipolar transistor (HBT) small-signal equivalent-circuit parameter-extraction procedure employing multibias S-parameter data is presented. The algorithm combines analytical and empirical parameter evaluation techniques and results in a bias-dependent HBT model. To minimize the risk of nonphysical parameter estimation, elements such as the DC transport factor, α_o, and the emitter-base conductance are evaluated from the device DC characteristics, and the frequency dispersion of α is related to the RC time-constant of the emitter-base junction. Moreover, initial values for the extrinsic device parasitics are obtained from “hot” as well as “cold” S-parameter data. The method results in excellent fit between measured and modeled S-parameter data in the frequency range DC-40 GHz and for a wide range of bias operating points     

K-band HBT and HEMT monolithic active phase shifters using vector sum method

Two monolithic 3-bit active phase shifters using the vector sum method to K-band frequencies are reported in this paper. They are separately implemented using commercial 6-in GaAs HBT and high electron-mobility transistor (HEMT) monolithic-microwave integrated-circuit (MMIC) foundry processes. The MMIC HBT active phase shifter demonstrates an average gain of 8.87 dB and a maximum phase error of 11/spl deg/ at 18 GHz, while the HEMT phase shifter has 3.85-dB average measured gain with 11/spl deg/ maximum phase error at 20 GHz. The 20-GHz operation frequency of this HEMT MMIC is the highest among all the reported active phase shifters. The analysis for gain deviation and phase error of the active phase shifter using the vector sum method due to the individual variable gain amplifiers is also presented. The theoretical analysis can predict the measured minimum root-mean-square phase error 4.7/spl deg/ within 1/spl deg/ accuracy.     

Direct parameter-extraction method for HBT small-signal model

An accurate and broadband method for the direct extraction of heterojunction bipolar transistor (HBT) small-signal model parameters is presented in this paper. This method differs from previous ones by extracting the equivalent-circuit parameters without using special test structures or global numerical optimization techniques. The main advantage of this method is that a unique and physically meaningful set of intrinsic parameters is extracted from the measured S-parameters for the whole frequency range of operation. The extraction procedure uses a set of closed-form expressions derived without any approximation. An equivalent circuit for the HBT under a forward-bias condition is proposed for extraction of access resistances and parasitic inductances. An experimental validation on a GaInP/GaAs HBT device with a 2×25 μm emitter was carried out, and excellent results were obtained up to 30 GHz. The calculated data-fitting residual error for three different bias points over 1-30 GHz was less then 2%     

异质结双极晶体管高频噪声建模及分析

提出了一个T等效异质结双极晶体管高频噪声电路模型.该模型是对通常用在硅双极晶体管中的Hawkins噪声模型进行改进得到的,主要的改进包括发射极理想因子、发射极电阻、内部BC结电容、外部BC结电容和其它寄生元素对器件噪声性能的影响.为了从等效噪声电路模型中计算出精确的噪声参数,采用了噪声相关矩阵法来计算噪声参数,从而避免了在等效电路变换中可能产生的简化和复杂的噪声测量.进一步利用该模型分析了等效电路元素对器件最小噪声系数的影响,分析计算结果和物理解释一致.同时通过基于异质结双极晶体管器件物理的公式,给出了器件参数对器件最小噪声系数的影响.     

Harmonic and two-tone intermodulation distortion analyses of theinverted InGa/InAlAs/InP HBT

Harmonic and two-tone intermodulation distortion analyses of the InGaAs/InAlAs/InP collector-up heterojunction bipolar transistor (HBT) are performed by a simple Ebers-Moll model. The parasitic elements of the equivalent circuit are extracted at zero bias by numerical optimization. A semianalytical approach is used to extract the intrinsic parameters of the small-signal equivalent circuit at nonzero bias points. Appropriate equations given by device physics are fitted to the bias variation of intrinsic parameters so that the Ebers-Moll model parameters can be extracted. Agreement between simulation and measurement of harmonic and intermodulation distortion is achieved     

Measurement of the temperature dependence of the I/SUB C/(V/SUB be/) characteristics of integrated bipolar transistors

The temperature dependence of the I/SUB C/(V/SUB be/) relationship of bipolar transistors can be characterized by two parameters /spl eta/ and V/SUB go/. The authors discuss a new method for the determination of these parameters. With this method there is no need for accurate temperature measurements. It is shown that the results fit very well with bandgap-reference temperature characteristics. An analytical method for the calculation of V/SUB g0/ and /spl eta/ from values of the base emitter voltage or the bandgap reference voltage at different temperatures is presented.     

GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs): optimization of fabrication process and epitaxial layer structure for high-efficiency high-power amplifiers

This paper describes a novel heterojunction bipolar transistor (HBT) structure, the collector-up tunneling-collector HBT (C-up TC-HBT), that minimizes the offset voltage V/sub CE,sat/ and the knee voltage V/sub k/. In this device, a thin GaInP layer is used as a tunnel barrier at the base-collector (BC) junction to suppress hole injection into the collector, which results in small V/sub CE,sat/. Collector-up configuration is used because of the observed asymmetry of the band discontinuity between GaInP and GaAs depending on growth direction. To minimize V/sub k/, we optimized the epitaxial layer structure as well as the conditions of ion implantation into the extrinsic emitter and post-implantation annealing. The best results were obtained when a 5-nm-thick 5/spl times/10/sup 17/-cm/sup -3/-doped GaInP tunnel barrier with a 20-nm-thick undoped GaAs spacer was used at the BC junction, and when 2/spl times/10/sup 12/-cm/sup -2/ 50-keV B implantation was employed followed by 10-min annealing at 390/spl deg/C. Fabricated 40/spl times/40-/spl mu/m/sup 2/ C-up TC-HBTs showed almost zero V/sub CE,sat/ (<10 mV) and a very small V/sub k/ of 0.29 V at a collector current density of 4 kA/cm/sub 2/, which are much lower than those of a typical GaInP/GaAs HBT. The results indicate that the C-up TC-HBT's are attractive candidates for high-efficiency high power amplifiers.     

A collector-up AlGaAs/GaAs heterojunction bipolar transistorfabricated using three-stage MOCVD

A new collector-up AlGaAs/GaAs heterojunction bipolar transistor (HBT) is reported. This structure is designed to minimize parasitic capacitance and to eliminate trenches for making contacts. The emitter, external base, and intrinsic base and collector have been grown in three stages using metalorganic chemical vapor deposition (MOCVD). The current gain of this collector-up HBT (C-up HBT) with a 5×14-μm² collector is 15     

Direct extraction of the AlGaAs/GaAs heterojunction bipolartransistor small-signal equivalent circuit

The authors describe a novel, direct technique for determining the small-signal equivalent circuit of a heterojunction bipolar transistor (HBT). The parasitic elements are largely determined from measurements of test structures, reducing the number of elements determined from measurements of the transistor. The intrinsic circuit elements are evaluated from y-parameter data, which are DC-embedded from the known parasitics. The equivalent-circuit elements are uniquely determined at any frequency. The validity of this technique is confirmed by showing the frequency independence of the extracted circuit elements. The equivalent circuit models the HBT s-parameters over a wide range of collector currents. Throughout the entire 1-18-GHz frequency range, the computed s-parameters agree very well with the experimental data     

A robust all-wet-etching process for mesa formation of InGaAs-InP HBT featuring high uniformity and high reproducibility

A simple InP-based heterojunction bipolar transistors (HBT) fabrication process featuring high uniformity and high reproducibility is introduced. No dry etching method was utilized for triple-mesa formation to avoid plasma damage to the device surface. An all-wet etching method was specially developed. This process is relatively simple compared to the conventional HBT fabrication process with respect to the emitter mesa formation by one-step selective etching. Uniformity of the current gain over a 3-in diameter wafer was approximately 2.9%, and the variation of the current gain of 17 wafers was 2.9 (max.-min.). The current gain cutoff frequency and the maximum oscillation frequency were 145 and 174 GHz, respectively. The mean time to failure was over 5 /spl times/ 10/sup 6/ h at 150/spl deg/ C whose criterion was over 3% changes in the current gain. This process is suitable for mass production of ultrahigh speed ICs in high yield.     

Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-/spl pi/ model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (R/sub bi/), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (g/sub m/), dynamic base-emitter resistance (r/sub /spl pi//), and base-emitter capacitance (C/sub /spl pi//) using the accurately extracted R/sub bi/. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs.     

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.