OEMCM中光互连布局算法的研究

本文着重于具有FSOI结构的OEMCM的光学互连及其布局算法研究.针对具有CGH的FSOI系统中的互连布局特点,提出一种有效互连布局算法.运用该算法对典型的大规模互连网络示例进行的运算结果表明,该算法不仅能够有效地解决这种FSOI系统中的网络互连具有一定空间局限性的问题,而且与已有的其它互连布局算法的计算机模拟结果相比,本文的算法在布局结果、算法的收敛性等方面具有明显的优点.     

OE MCM的自由空间光互连结构及其设计

现代集成电路系统采用的互连技术中,电互连和光互连各有优缺点,ＯＥＭＣＭ可以根据实际情况将二者的特点结合起来。目前国际上流行的自由空间光互连技术已经应用于异步传输模式和并行处理计算机结构中。着重介绍采用自由空间光互连ＯＥ ＭＣＭ的结构和设计考虑。     

自由空间光互连系统的结构和设计分析

光互连技术是光通信网络的基础。文章结合现代微电子系统中所采用的自由空间光互连技术,进行较全面的光互连结构和设计分析     

光互连的研究与新进展

讨论了集成电路向高集成度、高工作频率和更小特征尺寸发展时,常规金属互连存在的问题以及光互连对大系统如多芯片组件(MCM)、单芯片系统(SOC)等互连时的潜在优势。介绍了光互连发展中的几种新技术,太位自由空间转换加速器网络(FAST-Net)、选择性重复填充转移光刻组装(PL-pack with SORT)、自组织光波网络(SOLNET)、质子纵深成形(DLP)及光互连性能优化(带宽、功耗等)的研究,最后给出光互连所面临的一些问题并展望了其发展前景。     

三维自由空间光互连系统光学设计

现代科学技术,特别是通信和计算机技术迫切需要高性能巨型计算机(Supercomputer).随着集成电路技术的发展,依靠提高主频来提高系统性能,难度越来越大,目前比较一致的看法认为巨型机的发展趋势是发展大规模并行处理机(Massive Parallel Machine).特别是在天基一体星间通讯用的小型化星载高速大容量并行处理计算机系统中,传统的电互连由于存在通讯瓶颈、信号延迟、封装尺寸庞大等缺点而无法满足要求.三维自由空间多处理芯片光电子集成光互连交换网络模块在大容量、超小型方面优势明显.基于此,我们采用MESH光互连网络拓扑结构,设计了一种基于MESH网络的三维自由空间光互连集成模块,对系统内部结构进行了光学设计,并提出两种解决方案.根据设计的像差要求,对其中的透镜收发阵列进行了主光线追迹计算,确定了其最终结构,并详细比较了两种方案下的成像质量,结果表明直接由透镜中心斜入射法其出射信号弥散斑为0.4630 μm,能更好地满足三维自由空间MESH光互连网络光电子集成模块的要求.(PD9)     

光电MCM分割算法的改进

芯片级分割技术可用于解决光电MCM(OE MCM)物理设计所面临的散热、系统速度及最大光互连距离等问题.本文给出了光电MCM分割的模型,将经改进的遗传算法(Gas)用于光电MCM的分割问题中.改进算法较标准遗传算法更适合光电MCM分割,其应用可使系统功耗降低约50%.     

微透镜阵列和自由空间光互连

日本的RWC、欧洲的ESPITⅢ等，以计算机的高速化，并行化为目标的光互连应用研究正在积极进行中。光互连方式的研究也因通道数量而在波导型光互连和自由空间光互连方面分别进行。要想利用自由空间光互连进行大规模光交换和光运算的研究也很多。本文主要讨论实现自由空间光互连所需要的光学器件技术和集成组装技术。     

3-D MCM封装技术及其应用

介绍了超大规模集成电路（VLSI）用的3-D MCM封装技术的最新发展，重点介绍了3-D MCM封装垂直互连工艺，分析了3-D MCM封装技术的硅效率、复杂程度、热处理、互连密度、系统功率与速度等问题，并对3-D MCM封装的应用作了简要说明。     

半定制MCM基板设计专利简介

美国Microelectronics and Computer Technology Corporation(MCC)最近获得一项半定制MCM基板设计技术美国专利。被称为“快周期互连”(QTAI)的该专利技术具有加快MCM生产周期，降低成本的特点。     

高速多芯片组件的互连延迟

高速、高性能MCM中，往往把电路设计在欠阻尼小振荡输出的工作状态，以保持信号在互连传输线中的快速和平稳传播。已有文献关于互连延迟的研究往往是针对过阻尼或欠阻尼大振荡工作状态，即对应于通常的IC和PCB互连。即使对高速VLSI互连延迟的研究，考虑到计算的复杂性和有效性，也往往只处理过阻尼和欠阻尼大振荡两种状态，因此给出的结果如果用于研究MCM互连延迟，误差相当大甚至无效，文中讨论了一种研究MCM互连延迟的方法，并给出了延迟在三种工作状态下与各物理参数之间的确定关系式。     

基于功耗最小的光电多芯片组件优化划分算法

通过将光电MCM的功耗约束转化为光互连数最少的问题,建立了芯片级划分模型,解决了用遗传算法处理结构化设计的芯片级划分的问题,提出了基于功耗最小的光电MCM划分优化算法.实际的设计结果表明,该算法具有更强的寻优能力,比以往的算法更适合光电MCM的划分,可使系统功耗降低50%以上.     

Experimental evaluation of the 3-D optical shuffle interconnectionmodule of the sliding Banyan architecture

A free-space optical interconnection module for the sliding Banyan (SB) multistage interconnection network is experimentally evaluated. This three-dimensional (3-D) optical shuffle topology employs a macro-lens array in a reflective architecture. Interconnections for multiple stages are interleaved across a single two-dimensional (2-D) multichip array of “smart pixels”. The experimental module implements five interleaved stages of shuffle interconnections with approximately 10 μm resolution and 10 μm registration accuracy across a 10×10 cm, 256 node, simulated optoelectronic (OE) backplane. The experiments demonstrate the use of conventional refractive optical elements to implement the required shuffle interconnection pattern in a SB network. The results suggest that this reflective 3-D shuffle interconnected SB approach may lead to ATM switching fabrics with aggregate throughputs scaleable to >1 Tb/s. Such a system could be implemented with vertical cavity surface emitting laser (VCSEL) based smart pixel OE technology     

Description and evaluation of the FAST-Net smart pixel-basedoptical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 μm. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-μm pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks