一种10bit 200MS/s电流型DAC设计

基于SMIC 0.18μm CMOS工艺,采用了具有电荷抽放技术的电流源结构,以及新型锁存电路产生同步控制信号.设计了一个10位精度的数模转换器(DAC),电源电压为1.8 V,在50负载条件下,DAC满量程输出电流为4mA.当采样频率为200 MHz,输入频率为5 MHz的情况下.满量程功耗为15 mw.微分非线性误差(DNL)为0.25 LSB,积分非线性误差(INL)为0.15 LSB,无杂散动态范围达到79.7 dB.     

一种11位80MS/s分段式电流舵DAC的设计与验证

基于SMIC 0.13μm CMOS工艺,在3.3V/1.2V(模拟/数字)双电源下,设计了一种11位80MS/s的数/模转换器(DAC)。电路采用分段式电流舵结构,高6位为温度计码,低5位为二进制码。该DAC应用于无线通信SoC的模拟前端。IP核尺寸为960μm×740μm,功耗40mW,电路仿真结果显示,DAC的最大积分非线性误差和微分非线性误差分别为0.5LSB和0.3LSB。在20MHz输出信号频率和80MHz采样率下,DAC差分输出的SFDR为80dB。设计的电路已经通过MPW流片验证,给出了DAC芯片照片与实测数据。     

一种11位80 MS/s分段式电流舵DAC的设计与验证

基于SMIC 0.13 μm CMOS工艺,在3.3 V/1.2 V(模拟/数字)双电源下,设计了一种11位80 MS/s的数/模转换器(DAC)。电路采用分段式电流舵结构,高6位为温度计码,低5位为二进制码。该DAC应用于无线通信SoC的模拟前端。IP核尺寸为960 μm ×740 μm,功耗40 mW,电路仿真结果显示,DAC的最大积分非线性误差和微分非线性误差分别为0.5 LSB和0.3 LSB。在20 MHz输出信号频率和80 MHz采样率下,DAC差分输出的SFDR为80 dB。设计的电路已经通过MPW流片验证,给出了DAC芯片照片与实测数据。     

一种16位电流舵DAC的高精度前台校准方法

基于28 nm CMOS工艺,采用一种高精度的前台校准技术设计了一款16 bit电流舵数模转换器（Digitalto-analog converter,DAC）电路。该前台校准算法对16 bit数据对应的所有电流源进行校准,并且使用的电流源只有两种大小,降低校准难度的同时也提升了校准的精度。该校准电路引入了两种校准补充电流,分别用于温度和输出电流变化引起电流源失配的补偿,进一步减小了DAC电流源的失配,有效提高了DAC的整体性能。采用校准后,在-40～85℃温度范围内,微分非线性≤0.8 LSB,积分非线性≤2.0 LSB,200 MHz输出信号下无杂散动态范围≥75.3 dB。该校准方法提高了DAC的温度稳定性。     

Wuxi Branch of Southeast University, Wuxi Jiangsu 214028, China; 2.The 58th Institute of China Electronic Technology Company, Wuxi Jiangsu 214035, China

在研究高速D/A转换器的基础上,设计了一种5 V 10 bit高速分段式温度计码D/A转换器.设计的5-1-4温度计译码电路以及对版图布局的优化,使得DAC的DNL和INL最小,该电路的核心由三段式温度计编码控制的47个电流源构成.基于上华0.5μm工艺,采用HSPICE仿真工具对其进行仿真,得到在200 MHz的采样频率下对50 Ω负载满量程输出为45mA,非线性误差为DNL＜0.5LSB,INL＜0.75LSB.     

基于高精度电流源的10 bit电流舵DAC

文中设计了一款10 bit 250 MS/s的电流舵数模转换器(DAC),通过在DAC中引入阻抗增强型共源共栅电流源结构来提升DAC静态性能。整体电路采用了分段式电流舵结构,高6位为温度计码,低4位为二进制码。基于SMIC 28 nm CMOS工艺,对所设计的DAC进行了仿真验证,结果表明,在0.9 V电源电压下,DAC的积分非线性误差和微分非线性误差的最大绝对值分别为0.06 LSB和0.01 LSB;在输入频率为1.087 5 MHz,采样速率38.4 MS/s时,DAC的无杂散动态范围为65.3 dB;与传统相同性能的电流舵DAC相比,电流源单元的面积减少了约75%。     

一种嵌入式12位300 MHz D/A转换器

设计了一种用于高速频率合成器的12位300 MHz采样率嵌入式低功耗D/A转换器.该D/A转换器采用4+4+4分段式编码结构,用0.35 μm 2P4M CMOS工艺实现,整个模块面积仅为1.3 mm×1.2 mm.测试结果表明,在300 MHz采样率下,输出信号频率为30 MHz时,无杂散动态范围为64.22 dB,电路功耗仅为136 mW.     

一种新型电压电流混合加权12位DAC

设计并实现了一种双路12位电压输出型数模转换器(DAC)。采用“10+2”分段式结构,高10位采用开关树电阻串DAC架构,保证了DAC良好的单调性。低2位采用电流舵DAC架构,从整体上减小了DAC的面积。12位DAC未经修调即可实现12位转换精度。该DAC采用0.35 μm标准CMOS工艺实现,芯片尺寸为2.59 mm×2.09 mm。测试结果表明,在电源电压为5 V时,DAC的功耗为19.5 mW,DNL为-0.2 LSB,INL为-2.2 LSB,输出建立时间为2.5 μs。在采样频率为480 kS/s、输出频率为1 kHz的条件下,DAC的SFDR为65 dB。     

一种嵌入式10位2MS/s逐次逼近模数转换器

设计了一种10位2 MS/s嵌入式逐次逼近结构ADC。为提高ADC精度,其中DAC采用电压和电荷按比例缩放混合结构,比较器使用了输入失调校准和输出失调校准技术。采用TSMC0.18μm1P6M数字CMOS工艺进行流片验证,整个ADC核面积仅为0.9×0.6 mm2。测试结果表明,在2 MHz采样率、输入信号为180 kHz正弦信号情况下,该ADC模块具有8.51位的有效分辨率,最大微分非线性为-0.8~+0.7LSB,最大积分非线性为-1.7~+1.5 LSB,而整个模块的功耗仅为1.2 mW。     

应用于视频中的R2R梯形电阻网络DAC

本文设计了一款用于视频中的R2R梯形电阻网络数模转换器。其电路结构包含8位R2R梯形电阻网络DAC、输出放大器、低电平转高电平电路、模拟开关、参考电压和锁存器电路。电路设计是基于CSM0.11μm CMOS Logic工艺,经HSPICE仿真表明,DAC的积分非线性误差（INL）和微分非线性误差（DNL）分别小于1.65LSB和0.23LSB,功耗仅为3.86mW。     

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18 μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01 pV s. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33 LSB and a differential nonlinearity (DNL) of 0.14 LSB. The DAC can achieve a maximum measured SFDR of 65.19 dB for 97.50 kHz signal at a sampling rate of 100 MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07 MHz signal the measured SFDR is 56.84 dB at 100 MSPS sampling rate. At 50 MSPS sampling frequency and 146 kHz signal the SFDR of the DAC is 65.90 dB. The measured SFDR at 538 kHz signal is 63.62 dB for a sampling rate of 50 MSPS. Measured third order intermodulation distortion of the DAC is 58.55 dB, for a dual tone test with 1.03 MHz and 1.51 MHz signals at 50 MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06 MHz signal and 100 MSPS sampling frequency, the power dissipation of the DAC is 20.74 mW with 1.8 V supply.     

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.     

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2

A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-μm, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm². When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry     

基于40纳米CMOS工艺的500-MS/s 10-bit三通道电流舵型DAC的鲁棒性设计

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed.The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design.The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains.The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB.The measured SFDR at 1.7 MHz output signal is 58.91 dB,58.53 dB and 56.98 dB for R/G/B channels,respectively.The DAC has good static and dynamic performance despite the single-ended output.The average rising time and falling time of three channels are 0.674 ns and 0.807 ns.The analog/digital power supply is 3.3 V/1.1 V.This triple-channel DAC occupies 0.5656 mm2.     

一种GSM无线发射系统中的低功耗数模转换器

针对GSM标准无线发射系统中数模转换器(DAC)的要求,分析了影响其性能和功耗的限制因素,并在SMIC 0·13μm CMOS工艺1.2 V电源电压下设计了一款10位电流驱动型数模转换器(Current-steering DAC).使用最佳拟合线的算法衡量电流源匹配的随机误差对DAC静态非线性的影响,使得DAC的电流源...     

Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process

Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q~2 random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS samplin...     

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm²     

一个高线性13位流水线CMOS A/D转换器

介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性,自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5Ms/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.     

Power efficient high-speed DAC for wideband communication applications

This paper demonstrates a power efficient design of high-speed Digital-to-Analog Converters (DACs) for wideband communication systems. For Wireless personal area network applications with a 250 MHz signal bandwidth, a 6 bit DAC capable of two times the Nyquist rate sampling is implemented in a current steering segmented 2 + 4 architecture optimized for power efficiency. Along with a proposed master-slave deglitch circuit, several circuit techniques are investigated to improve dynamic performances such as linearity. Implemented in a 0.18 um CMOS process, our DAC achieved a superior conversion performance over the state-of-the-arts, exhibiting integral nonlinearity of less than 0.27 LSB and differential nonlinearity of less than 0.15 LSB. Measured spurious free dynamic range for 251 MHz output signal is 40.92 dB, with total power consumption at 1 GS/s of 6mW, yielding a figure-of-merits of 78.3 pJ/(conversion step*W).     

A 14-bit intrinsic accuracy Q2 random walk CMOS DAC

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q² random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-μm CMOS process. The die area is 13.1 mm²