一种用于过采样Σ-Δ A/D转换器的抽取滤波器

采用0.8 μm CMOS工艺,实现了一种用于过采样Σ-Δ A/D转换器的数字抽取滤波器.该滤波器采用多级结构,梳状滤波器作为首级,用最佳一致逼近算法设计的FIR滤波器作为末级,并通过位串行算法硬件实现.芯片测试表明,该滤波器对128倍过采样率、2阶Σ-Δ调制器的输出码流进行处理得到的信噪比为75 dB.     

蓝牙车载免提应用中回声消除功能的实现

回声问题是蓝牙免提应用系统中最常见而且无法避免的问题之一。通过对回声的产生和消除原理进行分析，研究了用于回声消除的自适应滤波算法。最后，利用BlueCore3-Multimedia蓝牙芯片内置的DSP实现了该算法，并根据车载应用环境的特点来调节算法参数，以使回声消除的效果达到最佳。     

一种0.35 μm CMOS高精度Σ-Δ A/D转换器

提出了一种应用于MEMS压力传感器的高精度Σ-Δ A/D转换器。该电路由Σ-Δ调制器和数字抽取滤波器组成。其中,Σ-Δ调制器采用3阶前馈、单环、单比特量化结构。数字抽取滤波器由级联积分梳状(CIC)滤波器、补偿滤波器和半带滤波器(HBF)组成。采用TSMC 0.35 μm CMOS工艺和Matlab模型对电路进行设计与后仿验证。结果表明,该Σ-Δ A/D转换器的过采样比为2 048,信噪比为112.3 dB,精度为18.36 位,带宽为200 Hz,输入采样频率为819.2 kHz,通带波纹系数为±0.01 dB,阻带增益衰减为120 dB,输出动态范围为110.6 dB。     

低功耗音频Δ -∑ D／A转换器

设计了一种适用于音频应用的16位D/A转换器.芯片集成了内插滤波器、Δ-Σ调制器和D类功放,可以独立完成带宽为8 kHz的音频数字信号到模拟信号的转换.内插滤波器完成64倍过采样并消除镜像信号,Δ-Σ调制器实现16位的转换精度.在驱动8 Ω负载时,D类功放实现97 dB的动态范围,最大输出功率达到100 mW,三次谐波小于-100 dB;同时,功率效率大于90%,特别适合低功耗应用领域.设计采用标准0.18 μm CMOS工艺,芯片面积约为2 μm×2 μm.     

低功耗音频Δ-Σ D/A转换器

设计了一种适用于音频应用的16位D/A转换器.芯片集成了内插滤波器、Δ-Σ调制器和D类功放,可以独立完成带宽为8 kHz的音频数字信号到模拟信号的转换.内插滤波器完成64倍过采样并消除镜像信号,Δ-Σ调制器实现16位的转换精度.在驱动8 Ω负载时,D类功放实现97 dB的动态范围,最大输出功率达到100 mW,三次谐波小于-100 dB;同时,功率效率大于90%,特别适合低功耗应用领域.设计采用标准0.18 μm CMOS工艺,芯片面积约为2 μm×2 μm.     

一种高性能Σ-Δ A/D转换器的设计

对于传统的Σ-Δ A/D转换器(ADC),其信噪比(SNR)随输入信号强度的减小而降低.文章根据自适应理论提出了一种自适应Σ-Δ ADC的解决方案及相应的电路实现.该电路设计充分考虑了在电路实现中误差的存在,给出了误差自校正电路.仿真结果表明,这种自适应Σ-Δ ADC的SNR几乎与输入信号的强度无关.     

基于MASH结构的24 bit Σ-Δ A/D转换器

设计了一种离散时间型24位Σ-Δ A/D转换器。该A/D转换器基于级联噪声整形(MASH)结构设计,整个转换器由前置可编程增益放大器、级联调制器和数字抽取滤波器等模块组成。该A/D转换器采用标准0.18 μm CMOS工艺实现,版图总面积为6 mm²。测试结果表明,在16 kS/s输出数据速率下,该A/D转换器的信噪比为106 dB,无杂散动态范围为110 dB,功耗仅为20 mW。     

一个18位高性能音频Σ-Δ数模转换器

本文介绍了一个采用多比特量化的高性能音频Σ-Δ数模转换器。相对于单比特量化的Σ-Δ DAC来说,多比特量化具有调制器环路设计简单、时钟频率低、杂波小等优点;而由多比特量化引入的失配误差,可以采用DWA误差整形算法,将其转换为高频段噪声外推到信号带外,使带内的噪底降低到单比特量化的水平。为减弱数模串扰,进行了对每个模拟元件都加上保护环的创新尝试。采用上述技术在0.18μm混合信号CMOS工艺上实现了一个18位DAC,芯片面积1.86 mm2。测试结果表明,数模转换器的信噪失真比(SNDR)和动态范围（DR）分别达到88dB和96dB。     

面向音频应用的可配置片上系统的设计与实现

基于一款通用的16位定点数字信号处理器,结合D/A转换器、A/D转换器和放大器等模拟电路模块,设计并实现了一种面向音频应用的可配置片上系统.该系统支持立体声输入输出,具有8～48 kHz之间可编程的采样频率,以及可编程的输入输出放大器增益.同时,设计使用了24位高精度Σ-Δ A/D转换器,并配有可供选择的数字滤波器.为支持不同应用,系统提供24位或16位的可编程字长调节.系统芯片工作在1.8 V电压下,芯片内各部分支持挂起或睡眠状态,有利于低功耗的便携式应用开发.介绍了部分关键功能模块的仿真、验证和测试,以及整个系统仿真模型的建立.     

一种应用于中频数字化接收的连续/离散时间混合结构带通Σ-Δ ADC

设计了一种应用于中频数字化接收的基于连续/离散时间混合结构带通Σ-Δ ADC。调制器采用六阶带通多比特量化结构,环路滤波器由两个连续时间谐振器和一个离散时间谐振器组成。采用电容数字校准技术将LC连续时间谐振器和RC连续时间谐振器的谐振频率校准至ADC中心频率f_clk/8。量化器采用3 bit Flash ADC实现。同时,使用数据加权平均算法对反馈DAC单元之间的失配进行校准。整体中频数字化接收机基于0.18 μm SiGe BiCMOS工艺设计。后仿真结果表明,在3.3 V电源电压下,当采样时钟频率f_clk为18 MHz且过采样率为45时,该Σ-Δ ADC消耗21 mW的功耗,在200 kHz的带宽范围内获得89 dB的信噪比和95 dB的无杂散动态范围。     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC.The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage.Experimental results show that for a 1.25 MHz @ -6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.     

A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW.<>     

基于BLSTM神经网络的回声和噪声抑制算法

考虑到非线性回声和非平稳噪声对智能设备回声消除算法的影响，论文提出一种基于双向长短时记忆(Bidirectional Long Short-Term Memory，BLSTM)神经网络的回声和噪声抑制算法。该算法首先采用多目标预处理模型，同步估计出回声和噪声信号的幅度谱；然后将其作为回声和噪声抑制模型的输入特征，进而估计出目标语音信号的理想比例掩模；最后通过联合训练两个模型得到最优回声和噪声抑制模型。实验结果表明，在非线性回声和非平稳噪声的环境下，该算法均取得了较好的回声和噪声抑制效果，语音失真较小。      

A 12-bit sigma-delta analog-to-digital converter with a 15-MHz clock rate

A sigma-delta analog-to-digital converter that achieves 12-bit integral and differential linearity and nearly 13-bit resolution without trimming is described. The baseband width is 120 kHz with a first filter pole at 60 kHz, the clock frequency is 15 MHz, and only one 5-V power supply is needed. The circuit was realized in a p-well CMOS technology with 3-/spl mu/m minimum feature size. Compared with previous sigma-delta modulators, the input signal frequency and clock rate limit have been increased by one order of magnitude. To achieve this increase, a novel integrator concept was developed using bidirectional current sources. The circuit is fully self-contained, requiring only a 15-MHz crystal and one blocking capacitor as external elements. This converter was developed as the analog front end of a digital echo cancellation circuit for an integrated services digital network.     

Single-chip A/D converter for digital microphones with on-chip preamplifier and time-domain noise isolation

A 1-bit sigma-delta modulator (ΣΔM) with an on-chip preamplifier for digital electret microphones has been implemented. A differential gm-opamp-RC preamplifier eliminates the traditional single-ended JFET interface and is integrated with an on-chip ΣΔM by removing all external components. The proposed time-domain noise isolation technique preserves circuit performance under a single power supply condition. The prototype implemented in a 0.18 μm CMOS technology achieves a 78 dB dynamic range and 62 dB peak signal-to-noiset distortion ratio (both A-weighted) with a current consumption of 450 μmA under a 1.8 V supply.     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

Acoustic echo cancellor with sub-band noise cancelling

An acoustic echo canceller with sub-band noise cancelling that employs a cascade configuration is proposed. The adaptation control adopted to match the occurrence of intermittent speech/echo and continuous room noise using the NLMS algorithm is very effective in echo and noise cancellation. Hardware is implemented and its performance evaluated through experiments. The noise cancellation significantly enhances overall echo-cancellation performance.<>     

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm², and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power     

Design of a high-order single-loop ∑△ ADC followed by a decimator in 0.18 μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital con verter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm~2.