MOSFET强表面场电学特性分析

本文考虑了横向电场和纵向电场对表面迁移率的影响,分析了强表面电场下MOSFET的电学特性.给出了电导和跨导等分析表达式.对硅VVMOSFET进行了电学特性的测量.实验结果与理论分析符合得很好.     

X波段砷化镓场效应晶体管的可靠性和失效模式分析

本报告中所用符号的定义 S.F.M. 扫描电子显微镜(以下简称扫描电镜) 直流参数 I_(DSS)——饱和漏电流;源接地,在5伏漏偏压下常规测量。 g_m——跨导;漏电流随栅偏压的变化。 V_p——夹断电压;将漏电流减小到10微安所需的栅压。 V_(f1),V_(f2)——分别为0.1毫安和1毫安电流时的栅二极管正向电压。 BV_(RGS)——反偏压栅二极管击穿电压;将源和漏短路在一起,在10微     

元件

1.8V的功率MOSFET Vishay旗下的Siliconix近日推出12个型号p沟道MOSFET,它们在V_(DS)=1.8V的导通电阻很低,例如Si4465DY在V_(DS)=1.8V时的导通电阻仅16mΩ、在V_(DS)=2.5V时为11mΩ、在V_(DS)=2.5V时仅9mΩ;在环境温度为70℃时的漏极电流可达±10A。封装:8脚SO、6脚TSOP和SOT-23。     

功率MOSFET参数测试仪的设计

功率MOSFET参数测试仪是用来测试功率MOSFET电特性参数的仪器设备（如阈值电压、跨导等）。以单片机为核心,介绍功率MOSFET参数测试仪的原理、设计及实现,设计了电特性参数测试的具体电路,编写了测试控制程序,通过对设计出的测试仪系统进行实验和调试,可以准确测量功率MOSFET的阈值电压、跨导、栅源漏电流、零栅压漏极电流及耐压。     

半导体电场敏感器件和电场传感器

本文介绍了用MOS工艺制作的直接栅电场敏感FET,对其敏感特性进行了实验研究和理论分析.室温下,用此器件在空气中检测电场时,在外加电场小于空气击穿场强的范围内,器件的电流-电场跨导大于2μA/(kV/cm).用直接栅FET和普通MOSFET作差分对,利用栅绝缘层上压降正比于外电场的原理,用反馈和差分放大组合电路制作电场传感器.得到了0.2V/ (kV/cm)的线性输出.     

掺杂分布对EPROM编程的影响

在EPROM器件中,栅注入电流Ig对于Si表面的可动电子浓度n和电场E非常敏感。我们用二维电子温度器件模拟程序研究了n、E和Ig与掺杂分布的关系。 我们研究了沟长L=2(μm)、浮置栅氧化层厚度T_(ox)=400(?)的双栅EPROM器件。漏极写入电压采用17V,产生的漏电流为1.2mA。我们在一个等效的MOSFET上调节栅电压,以便使漏电流I_d与这一写电流相等,发现三种不同的沟道分布的浮置栅压(V_(gf))当量为12.8V、13.9V和16V。     

宽温区MOSFET的非常数表面迁移率效应

在对硅材料基本物理参数的高温模型和宽温区 ( 2 7～ 30 0℃ ) MOSFET基本特性深入研究的基础上 ,进一步研究了宽温区 MOSFET的非常数表面迁移率效应。理论和实验研究结果表明 ,由于高温下晶格散射加剧 ,使表面纵向电场对载流子迁移率的影响减弱 ,使小尺寸 MOSFET横向电场引起的载流子饱和速度下降     

基于陷阱的4H-SiC MESFET频散效应分析

在建立正确模型的基础上,运用ISE软件的二维仿真,模拟了4H-SiC MESFET在交流小信号条件下,表面陷阱和体陷阱对跨导和漏电导随频率变化的影响。分析了产生频散效应的原因以及内部机理,同时考虑了不同环境温度对跨导的频散影响。结果表明,在低频条件下,陷阱会导致跨导和漏电导频散,漏电压越大,环境温度越高,频散越不明显。     

GaAs电学参数温度性质的研究

本文用表面光伏方法和计算机拟合技术,在21—320K温度范围内得到N-GaAs的重要电学参数L_p、μ_p、n_0、S和V_(SO)的温度关系曲线。通过对这些温度关系曲线的理论分析和拟合计算,进一步得到样品的施主杂质浓度N_D、杂质电离能ε_D、基态简并度g_D和杂质补偿度K_I的数值,少子迁移率μ_p(T)的经验公式和表面费米能级E_(FS)的温度关系曲线。文中还推导了有关的理论公式。     

22nm技术节点异质栅MOSFET的特性研究

研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。     

Semi-empirical equations for electron velocity in silicon: Part I—Bulk

A simple semi-empirical equation for the electron drift velocity in silicon as a function of electric field and temperature is derived from elementary physical assumptions. The parameters in this equation, namely the low field mobility, effective mass, and optical phonon energy, are well defined physical quantities, Excellent agreement with the empirical Scharfetter-Gummel equation is obtained. The temperature dependence of the saturation velocity and the warm electron coefficient β are also well described. A field dependent mobility scaling factor is derived to account for the steeper rise of the velocity-field profile in doped silicon which results from decreased coulombic scattering of hot carriers. The longitudinal electron diffusion is also crudely predicted.     

Accumulation-layer surface-wave convolver

A new type of coupled silicon?lithium-niobate convolver is reported, in which a known accumulation layer of electrons was produced at the silicon surface. By applying a normal electric field, the electron density was varied, and the convolution signal was a strong function of this surface charge density.     

Challenges in SiC power MOSFET design

The impact of fundamental and technological parameters is considered for SiC power MOSFETs. The wide bandgap nature of SiC increases the surface electric field by 2× at inversion compared to silicon, placing an important role on surface roughness in reducing the field-effect mobility. The presence of interface-trapped charges also acts to reduce the channel mobility and increases the sensitivity of the threshold voltage to temperature. The high critical electric field of SiC increases the stored energy in the switch output capacitance by 10× compared to silicon. For hard-switched converters, it is important to design SiC MOSFETs with a high saturation current to enable high-speed turn-on transients required to discharge the integral drain-source capacitance.     

硅基(Pb,La)(Zr,Ti)O_3反铁电厚膜的制备及介电性能

采用溶胶–凝胶工艺制备了具有高度(100)择优取向的(Pb,La)(Zr,Ti)O3反铁电厚膜(厚约2.2μm)。研究了该反铁电厚膜在不同温度下的电场诱导相变效应和不同电场强度下的温度诱导相变效应。结果表明:(Pb,La)(Zr,Ti)O3反铁电厚膜在室温下处于反铁电态;随着温度升高,厚膜的相变开关电场强度逐渐降低,反铁电态越来越不稳定,当温度高于132℃且电场强度为0 kV/cm时,厚膜处于顺电态;随着外加电场强度的增大,厚膜的AFE(反铁电态)-FE(铁电态)相变温度向低温方向漂移,当电场强度大于164 kV/cm时,厚膜在室温下已处于铁电态。     

纳米多孔硅的场致电子发射性能研究

对采用阳极氧化法及阴极还原表面处理技术制备的性能稳定的纳米多孔硅,用原子力显微镜(AFM)表征了其微观结构,多孔硅颗粒粒径在30 nm左右.室温条件下测试了多孔硅场电子发射的特性,结果表明,多孔硅具有很好的场致发光性能,在5 V/μm的电场下就可以产生场发射电流.多孔硅的开启电压在1 000 V左右,发射电流随着电压的增大而不断增大,发射电压在2 000 V以上.

Abstract：

Nanoscale porous silicon (PS) was prepared by anodic oxidation, cathode reduction and surface treatment technique. The porous silicon particles with the average diameter of about 30 nm were obtained by characterizing their microstructure with atomic force microscope (AFM). Electron field emission characteristics of porous silicon were investigated at room temperature. The resuhs demonstrate that porous silicon has favorable electroluminescence properties, and the field emission current can be generated only under the electric field of 5 V/ μm. And the turn - on voltage is about 1 000 V. With the increase of the offered voltage, the emission current is enhanced and the emission voltage is over 2 000 V.     

Measurement of high-field electron transport in silicon carbide

We report recent measurements of the drift velocity of electrons parallel to the basal plane in 6H and 4H silicon carbide (SiC) as a function of applied electric field. The dependence of the low field mobility and saturated drift velocity on temperature are also reported. The saturated drift velocities at room temperature are approximately 1.9×10⁷ cm/s in 6H-SiC and 2.2×10⁷ cm/s in 4H-SiC     

非绝热近场光学诱导平滑硅表面微结构的电场模拟

如何进一步降低超光滑光学元件表面缺陷是现代超精密光学元件制作技术研究的热点之一。在传统抛光方法的基础上,引入非绝热近场光学诱导平滑硅表面微结构这一新型方法,进一步去除超光滑抛光表面残留的纳米级表面微缺陷,降低表面粗糙度。通过建立超光滑硅表面的微结构几何模型,采用时域有限差分法对表面微结构凸起在532 nm 激光作用下的局域电场增强进行数值模拟。对比不同尺度的微结构所激发的最大电场强度表明,在基底峰谷值小于25.5 nm 时,随微结构尺度递增,所激发的局域电场强度最大值约呈线性增长;随微结构倾斜率的逐渐递增,电场强度最大值也呈递增趋势。通过对激光诱导表面微结构调制电场的数值模拟,构建了硅表面微结构诱导平滑的物理图像,为描绘激光辐照下非绝热近场光学诱导平滑表面微结构的物理过程提供了有力的理论支持。     

Measurements of charge carrier mobilities and drift velocity saturation in bulk silicon of 〈1 1 1〉 and 〈1 0 0〉 crystal orientation at high electric fields

The mobility of electrons and holes in silicon depends on many parameters. Two of them are the electric field and the temperature. It has been observed previously that the mobility in the transition region between ohmic transport and saturation velocities is a function of the orientation of the crystal lattice.This paper presents a new set of parameters for the mobility as function of temperature and electric field for 〈1 1 1〉 and 〈1 0 0〉 crystal orientation. These parameters are derived from time of flight measurements of drifting charge carriers in planar p⁺nn⁺ diodes in the temperature range between −30 °C and 50 °C and electric fields of 2 × 10³ V/cm to 2 × 10⁴ V/cm.     

A theory of enhanced impact ionization due to the gate field and mobility degradation in the inversion layer of MOSFET's

A new explanation of carrier heating within silicon inversion layers is offered which is in full accordance with classical laws. We show that, as is usually assumed, the heating is due to the longitudinal electric field. However, also the transverse field influences the electron temperature by determining the minimum kinetic energy and therefore influencing the electron mobility. In this way the distribution function is heated above that in bulk material as witnessed by the significant increase in measured noise figures and in the calculated electron impact ionization rate.     

Degradation of silicon dioxide during selective silicon epitaxy in a dichlorosilane environment

The electrical degradation of dry thermal SiO₂ upon exposure to selective silicon epitaxy using dichlorosilane has been investigated. Capacitors were fabricated with thermal gate oxides (120 to 440A thick) grown on p-type silicon (100) substrates. Prior to the gate electrode formation, the oxides were exposed to hydrogen and dichlorosilane + hydrogen anneals. Leakage current and electric field breakdowns were measured to evaluate the effects of these anneals on the SiO₂ degradation. The SiO₂ degradation occurring because of dichlorosilane exposure was studied as a function of the temperature and time. While dichlorosilane exposure at temperatures above 850°C was found to cause high leakage current and breakdowns at low electric fields for silicon dioxide films thinner than 440Å, little effect was observed as a result of hydrogen and chlorine exposures. The degradation mechanism was attributed to pinhole etching via volatile SiO formation along defects present in the as-grown SiO₂.