Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

Do chip size limits exist for DCA?

Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

Procedure for design optimization of a T-cap flip chip package

In this study, a 1/4 three-dimensional finite element model of a T-cap flip chip package containing the substrate, underfill, solder bump, silicon die, metal cap and cap attachment was established to conduct thermo-mechanical reliability study during the flip chip fabrication processes. The applied thermal load was cooled from 183 °C to ambience 25 °C to determine the thermal stress and warpage during the curing period of solder ball mounting process. Under fixed geometry, two levels of underfill, metal caps and cap attachments were used to conduct the 2³ factorial design for determining reliable material combinations. The statistical tests revealed that the significant effects affecting the thermal stress were the underfill, metal cap, cap attachment and the interaction between the underfill and cap attachment. The metal cap, cap attachment and their interaction significantly affected the warpage. The proposed regression models were used to perform the surface response simulations and were useful in selecting suitable materials for constructing the package. This study provides a powerful strategy to help the designer to easily determine reliable packaging structures under various reliability considerations.     

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.     

倒装芯片下填充工艺的新进展（二）

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

倒装芯片下填充工艺的新进展（一）

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

Package design and materials selection optimization for overmolded flip chip packaging

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages.     

Adhesion characterization of no-flow underfills used in flip chipassemblies and correlation with reliability

Adhesion is one of the key properties of underfills used in flip chip assemblies. This paper characterizes the adhesion strengths of no-flow underfill materials to various die passivations using the shear test techniques. A novel shear test vehicle with planner underfill layers between the die and substrate is presented. The adhesion strengths and failure modes of the no-flow underfill materials during shear testing correlate well with their thermal shock reliability test results. Underfill adhesion related failures such as delamination and crack are investigated and correlated between flip chip assemblies and shear test vehicle assemblies without solder joint interconnects     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

Underfilling fine pitch BGAs

Fine pitch BGAs and chip scale packages have been developed as an alternative to direct flip chip attachment for high-density electronics. The larger solder sphere diameter and higher standoff of CSPs and fine pitch BGAs improve thermal cycle reliability while the larger pitch relaxes wiring congestion on the printed wiring board. Fine pitch BGAs and CSPs also allow rework to replace defective devices. Thermal cycle reliability has been shown to meet many consumer application requirements. However, fine pitch BGAs and CSPs have difficulty passing mechanical shock and substrate flexing tests for portable electronics applications. The fine pitch BGA used in the study was a 10 mm package with the die wire bonded. The package substrate was bismaleimide-triazine (BT) and the solder sphere diameter was 0.56 mm. Two types of underfill were examined. The first was a fast flow, snap cure underfill. This material rapidly flows under the package and can be cured in five minutes at 165°C using an in-line convection oven. The second underfill was a thermally reworkable underfill for those applications requiring device removal and replacement. The paper discusses the assembly and rework process. In addition, liquid-to-liquid thermal shock data is presented along with mechanical shock and flexing test results     

Dependence of Flip Chip Solder Reliability on Filler Settling

Thermomechanical reliability of solder joints in flip-chip packages is usually analyzed by assuming a homogeneous underfill ignoring the settling of filler particles. However, filler settling does impact flip chip reliability. This paper reports a numerical study of the influence of filler settling on the fatigue estimation of flip-chip solder joints. In total, nine underfill materials ( 35 vol% silica filler in three epoxies with three filler settling profiles for each epoxy) are individually introduced in a 2-D finite element (FE) model to compare the thermal response of flip chip solder joints that are surrounded by the underfill. The results show that the fatigue indicators for the solder joints (inelastic shear strain increments and inelastic shear strain energy density) corresponding to a gradual, nonuniform filler profile studied in this paper can be smaller than those associated with the uniform filler profile, suggesting that certain gradual filler settling profiles in conjunction with certain resin grades may favor a longer solder fatigue lifetime. The origin of this intriguing observation is in the fact that the solder fatigue indicators are a function of the thermal mismatch among the die, substrate, solder, and underfill materials. The thermal mechanics interplayed among these materials along with a gradual filler profile may allow for minimizing thermal mismatch; and thus lead to lower fatigue indicators.      

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.