Electrical characteristics of high-quality sub-25-Å oxidesgrown by ultraviolet ozone exposure at low temperature

We have developed a method for controllably and reproducibly growing self-limiting ultrathin oxides with excellent electrical properties in the range ~10-25 Å thick at temperatures ranging from 25 to 600°C, respectively, using an ultraviolet ozone (UVO₃) oxidation process. The self-limiting thickness depends primarily on the substrate temperature, allowing ultrathin oxide growth with precision and reproducibility using this UVO₃ process. Oxides grown by this method are comparable in electrical quality to thermal oxides, with similar leakage current densities and breakdown fields E_BD>10 MV/cm. Current-voltage (I-V) analysis shows oxide thickness uniformity to within 1% from center to edge of a 4-in wafer. Capacitance-voltage (C-V) characterization of ~25 Å oxides shows excellent saturation behaviour, with low midgap interface trap densities and no hysteresis or dispersion     

Capacitance-Voltage measurement method for ultrathin gate dielectrics using LC resonance circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.     

Capacitance-voltage characterization of fully silicided gated MOS capacitor

This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leak-age current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic, A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

Estimating oxide thickness of tunnel oxides down to 1.4 nm usingconventional capacitance-voltage measurements on MOS capacitors

High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm     

Tunneling through ultrathin GaAs n++-p++-n++ barrier grown by molecular layer epitaxy

The I-V characteristics of ultrathin GaAs n⁺⁺-p⁺⁺ -n⁺⁺ barrier structures with a 45 Å thick p⁺⁺ layer grown by molecular layer epitaxy (MLE) have been measured at room temperature and 77 K. The tunneling probability for this structure has been calculated as a function of effective tunneling width. It was found that good agreement between experiment and calculation is obtained when the effective tunneling width is assumed to be 75 Å, which is much smaller than the depletion width about 190 Å measured by C-V method. This fact indicates that the depletion width approximation cannot be used to measure the exact tunneling width for ultrathin barrier devices     

Cyclic current-voltage characterization applied to edge damageevaluation in gate definition plasma etching

A simple two-terminal cyclic current-voltage (I-V) measuring approach is used to monitor damage in gate definition plasma etching of poly-Si gate 70 Å oxide MOS structures. This new technique is used to identify the presence of trapping and near-surface silicon substrate generation lifetime changes due to edge exposure     

A dual-mechanism solid-state carbon-monoxide and hydrogen sensor utilizing an ultrathin layer of palladium

Pd-gate MOS sensors were fabricated on p-type silicon wafers. The gate films were 25 and 40 Å thick with an oxide thickness of 100 Å. Contacts were made to allow measurement of the MOS capacitance and of the impedance across the gate film. Voltage shifts in the MOS C-V curves and shifts in the Pd film impedance were measured as functions of 1) the concentration of CO and H2; 2) time as the gas ambient was varied. The devices showed sensitivity to H2at room temperature and to CO and H2at elevated temperatures. When the 25-Å device was exposed to 300 ppm H2in air at room temperature, the C-V curve shifted by -430 mV and the impedance decreased by 20 ω or 5 percent. When the 25-Å device was exposed to 5000 ppm CO in air at 150°C, the C-V curve shifted - 200 mV and the impedance decreased by 140 ω (10 percent). When exposed to 0.1-percent H2in argon, the resistance of the 40-Å device increased by about 2 percent. When measured as a function of time, the changes in MOS capacitance tend to track the changes in impedance. An effect similar to hydrogen-induced drift (HID) was observed for CO at elevated temperature.     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Reduction in leakage current of low-temperature thin-gate oxide byrepeated spike oxidation technique

A novel repeated spike oxidation (RSO) technique had been used to grow low-temperature thin-gate oxide. Around the similar effective oxide thickness extracted from the capacitance-voltage (C-V) curves under quantum mechanical effect consideration, the leakage currents of RSO samples were near one order of magnitude lower than those of typical ones. Flat band voltage shift or electron trapping in RSO oxides during current-voltage (I-V) measurement had not been observed. The reduction of interface state densities and the improvement in oxide uniformity would be the possible reasons for the reduction in leakage currents of RSO samples     

Chemical reaction concerns of gate metal with gate dielectric in Tagate MOS devices: an effect of self-sealing barrier configurationinterposed between Ta and SiO2

Chemical reaction of gate metal with gate dielectric for Ta gate MOS devices has been experimentally investigated both by electrical and physical measurements: capacitance-voltage (C-V), current-voltage (I-V), transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron diffraction measurements. In spite of the chemical reaction of Ta with SiO₂ consuming ~1-nm-thick in gate oxide, the interface trap densities of ~2×10¹⁰ cm^-2 eV ^-1 at midgap and ideal channel mobility characteristics have been observed in the Ta gate MOS devices with 5.5-nm-thick thermal oxide gate dielectric. Considering the experimental data with theoretical calculation based on thermodynamics together, a barrier layer model has been developed for the Ta gate MOS systems. The physical mechanism involved is probably self-sealing barrier layer formation resulting from the chemical reaction kinetics in the free-energy change of Ta-Si-O system     

The characterization of a proposed model GaAs/anodic oxide interface

The n-GaAs/anodic oxide interface has been characterized using capacitance-voltage (C-V) measurements on MOS capacitors and current-voltage (I-V) measurements on Schottky barriers. A simple interface state model cannot explain the observed behavior. Schottky barrier measurements made on surfaces which were previously anodized with the oxide layer subsequently removed by etching show evidence for the presence of a compensated layer in the anodized semiconductor surface region. This leads to a maximum in the conduction band energy near the surface, and based on these observations a quantitative model is formulated which can partially explain some aspects of the GaAs/anodic oxide interface, including the accumulation mode capacitance dispersion observed by many authors. Further studies were made in which the oxides were grown to difference thickness and then etched to the same thickness. Measurements on these oxides show that the C-V dispersion is related to the current density during growth and to the thickness of the oxide. There is also a correlation between the temperature during oxide growth and the interface properties. Oxides grown at 65°C show significantly more dispersion than oxides grown at 0°C. The temperature during anodization is also found to influence the anodization constant. This work was supported by a research grant (ENG-76-81334) from the National Science Foundation, Washington, DC.     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

Determination of deep ultrathin equivalent oxide thickness (EOT)from measuring flat-band C-V curve

In this letter, a novel and simple method to determine deep ultrathin oxide thickness by measuring the MOS capacitance under the flat-band condition is reported. The mechanism of this method has been profoundly studied. The results determined by this method show good agreement with those using capacitance-voltage (C-V) simulation, ellipsometer, and high-resolution transmission electromicroscopy (HRTM) analysis for thin oxides (2~3 nm). The thickness of pure oxide extracted by this method in this experiment can be down to 1.4 nm despite the obvious C-V distortion     

Electrical characteristics of MOSFETs using low-pressurechemical-vapor-deposited oxide

The electrical characteristics of MOSFETs and MOS capacitors utilizing thin (80-230 Å) low-pressure chemical-vapor-deposited (LPCVD) oxide films deposited at 12 Å/min are presented. MOSFETs using CVD oxides show good electrical characteristics with 70-90% of the surface mobility of conventional MOSFETs. The CVD oxides exhibit the same low leakage current and high breakdown fields as the thermal oxides, and significantly lower trapping and trap generation rates than thermally grown oxides. Interface state densities of ⩽3×10¹⁰ cm^-2 eV^-1 are obtained from CVD devices by using a short annealing in oxygen ambient following the deposition. These results indicate that these LPCVD oxide films may be promising dielectrics for MOS device application     

Edge-defined patterning of hyperfine refractory metal silicide MOS structures

Edge-defined patterning was used to obtain hyperfine (< ¼ µm) refractory metal silicide MOS structures. A patterning technique, using standard optical lithography and advanced etching technology, was developed and proven to result in submicrometer structures of controllable dimensions. Hyperfine MoSi2/SiO2/Si MOS structures were realized using a vertical aluminum step defined by CCl4plasma etching. The MoSi2patterning was performed using anisotropic planar etching in NF3. Functional relationships between Al step height (0.3- 0.9 µm), MoSi2film thickness (0.3-1.0 µm), and the resulting silicide linewidth (0.1-0.25 µm) and line height (0.3-0.9 µm) were investigated. It was found that the linewidth and height could be independently controlled.     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

Fabrication of a novel MOS diode by indium incorporation control for microelectronic applications

Control of the electronic parameters on a novel metal-oxide-semiconductor (MOS) diode by indium doping incorporation is emphasized and investigated. The electronic parameters, such as ideality factor, barrier height (BH), series resistance, and charge carrier density are extracted from the current-voltage (I-V) and the capacitance-voltage (C-V) characteristics. The properties of the MOS diode based on 4%, 6% and 8% indium doped tin oxide are largely studied. The Ag/SnO₂/nSi/Au MOS diode is fabricated by spray pyrolysis route, at 300℃ from the In-doped SnO₂ layer. This was grown onto n-type silicon and metallic (Au) contacts which were made by thermal evaporation under a vacuum@10^-5 Torr and having a thickness of 120 nm and a diameter of 1 mm. Determined by the Cheung-Cheung approximation method, the series resistance increases (334-534 Ω)with the In doping level while the barrier height (BH) remains constant around 0.57 V. The Norde calculation technique gives a similar BH value of 0.69 V but the series resistance reaches higher values of 5500 Ω. The indium doping level influences on the characteristics of Ag/SnO₂:In/Si/Au MOS diode while the 4% indium level causes the capacitance inversion and the device turns into p-type material.     

Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).     

A capacitance-based method for experimental determination ofmetallurgical channel length of submicron LDD MOSFETs

A capacitance based method for determining L_met the metallurgical channel length of MOSFET, is proposed in this paper. This method has been extensively evaluated via two-dimensional numerical device simulation of MOSFETs with different source/drain tip and channel impurity concentration profiles as well as different gate oxide thicknesses. For all the impurity profiles tested, results demonstrated that the accuracy in extracting L_met of MOSFETs with gate oxides thinner than 100 Å is better than 110 Å. This method is applicable even when there is significant source/drain reoxidation induced gate oxide thickening, as long as the gate oxide thickening is not extended into the region directly above the metallurgically defined channel region. Unlike the determination of L_eff, the effective electrical channel length, from the drain current, L_met is extracted from capacitance data and the extraction is free from complications that can be introduced by incomplete removal of the resistive effects associated with contacts and the lightly doped source/drain region. Extensive measurements were performed on MOSFETs of different technologies. It is shown that the measurement is accurately repeatable and no device stressing is experienced over the required bias range. The L_met and L_eff extracted from measured capacitance and drain current data are compared. Results showed that L _met is typically 700 to 1200 Å shorter for submicron MOS technologies, but it tracks with L_eff, i.e. a shorter L _met corresponds to a shorter L_eff