Parallel,self-organizing,hierarchical neural networks with forward-backward training

A forward-backward training algorithm for parallel, self-organizing hierarchical neural networks (PSHNNs) is described. Using linear algebra, it is shown that the forward-backward training of ann-stage PSHNN until convergence is equivalent to the pseudo-inverse solution for a single, total network designed in the least-squares sense with the total input vector consisting of the actual input vector and its additional nonlinear transformations. These results are also valid when a single long input vector is partitioned into smaller length vectors. A number of advantages achieved are: small modules for easy and fast learning, parallel implementation of small modules during testing, faster convergence rate, better numerical error-reduction, and suitability for learning input nonlinear transformations by other neural networks. The backpropagation (BP) algorithm is proposed for learning input nonlinearitics. Better performance in terms of deeper minimum of the error function and faster convergence rate is achieved when a single BP network is replaced by a PSHNN of equal complexity in which each stage is a BP network of smaller complexity than the single BP network.     

Concurrent error detection in highly structured logic arrays

Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques.     

Error Correction Schemes with Erasure Information for Fast Memories

Two error correction schemes are proposed for word-oriented binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the correction capability of an error-correcting code (ECC). The proposed schemes enable the correction of double-bit errors based on the combination of erasure information with single-bit error correction and double-bit error detection (SEC-DED) codes or shortened (SEC) codes. The correction of single-bit errors is always guaranteed. Ways to increase the number of double-bit and triple-bit errors that can be detected by shortened SEC and SEC-DED codes are considered in order to augment the error correction capability of the proposed solutions.     

随机petri网分析分组交换网中窗式流量控制机理

本文将随机Ｐｅｔｒｉ网与排队论相结合，对分组交换网中的窗式流量控制机理进行了描述与分析，建立了窗式流量控制机理的随机Ｐｅｔｒｉ网模型，并给出了随机Ｐｅｔｒｉ网模型的可达图及状态转移方程。为通信网的性能分析和评价提供了一种新的方法。     

Fault tolerance in computing, compressing, and transmitting FFTdata

Remote-sensing applications often calculate the discrete Fourier transform of sampled data and then compress and encode it for transmission to a destination. However, all these operations are executed on computing resources potentially affected by failures. Methods are presented for integrating various fault detection capabilities throughout the data flow path so that the momentary failure of any subsystem will not allow contaminated data to go undetected. New techniques for protecting complete source coding schemes are exemplified by examining a lossy compression system that truncates fast Fourier transform (FFT) coefficients to zero, then compresses the data further by using lossless arithmetic coding. Novel methods protect arithmetic coding computations by internal algorithm checks. The arithmetic encoding and decoding operations and the transmission path are further protected by inserting sparse parity symbols dictated by a high-rate convolutional symbol-based code. This powerful approach introduces limited redundancy at the beginning of the system but performs detection at later stages. While the parity symbols degrade efficiency slightly, the overall compression gain is significant because of the run-length coding. Well-known fault tolerance measures for FFT algorithms are extended to detect errors in the lossy truncation operations, maintaining end-to-end protection. Simulations verify that all single subsystem errors are detected and the overhead costs are reasonable     

Probability of correctness of processor-array outputs usingperiodic concurrent error detection

Processor arrays, featuring modularity, regular interconnection, and high parallelism, are well suited for VLSI/WSI implementation and specific applications with high computational requirements. Error detection and recovery are important for some applications of processor arrays. Concurrent error detection (CED) techniques, which check normal system operations, are designed to detect errors caused by transient and intermittent faults, However, CED techniques typically suffer from costly hardware penalties or performance costs. This paper describes the periodic application of concurrent error detection (PACED) technique which allows the performance costs incurred through the use of time-redundant CED in processor array architectures to be reduced. The application of CED is varied in both time and space to provide probabilistic detection of errors in processor arrays. The probability of correctness of outputs from processor arrays is studied. Formulae are derived that predict, upon error detection, the amount of possibly erroneous output, for single processors, linear arrays and 2-dimensional mesh processor arrays. The results indicate that the error coverage can be surprisingly high when PACED is applied in processor arrays, e.g., 95% for checking performed 50% of the time     

Generalized Bose–Lin Codes, a Class of Codes Detecting Asymmetric Errors

Bose and Lin introduced a class of systematic codes for detection of binary asymmetric errors. In this note, we describe a generalization to q-ary asymmetric error detecting codes. For these codes, the possible undetectable errors are characterized and the undetectable errors of minimum weight are determined     

Fast algorithms for erasures and error correction in redundant residue number systems

In this work, we extend the coding theory approach to error control in redundant residue number systems (RRNS). The concept of erasure correction capability in RRNS is introduced. We derive the relationship between the minimum distance and the error detection and error/erasure correction capability. New computationally efficient algorithms are derived for simultaneously correcting single errors and multiple erasures and detecting multiple errors. These algorithms reduce the computational complexity of the previously known algorithms by at least an order of magnitude. Another attractive feature of the algorithms is that all the arithmetic operations are modulo operations. Consequently, the need to process large valued integers is avoided.     

The Newton radius of codes

For a binary linear code C of minimum distance d, if t>(d-1)/2, then there are errors of weight t which are not uniquely correctable. However, in many cases there are also errors of weight t which are uniquely correctable. The Newton radius of a code is defined to be the largest weight of a uniquely correctable error. Bounds and exact values of the Newton radius are given for several classes of codes     

Decoding real-number convolutional codes: change detection, Kalmanestimation

Convolutional codes which employ real-number symbols are difficult to decode because of the size of the alphabet and the numerical and roundoff noise inherent in arithmetic operations. Such codes find applications in both channel coding for communication systems and in fault-tolerance support for signal processing subsystems. A new method for error correction based on optimum mean-square recursive Kalman estimation techniques incorporates time-varying models for the system and associated disruptive noise sources. The underlying common model for communications and fault tolerance applications assumes the system operates nominally with low levels of channel or numerical and roundoff noise, occasionally experiencing temporarily larger noise statistics. A time-varying Kalman estimation structure which uses single-step and fixed-lag smoothing predictors can correct errors to within the nominal low-noise levels. Correction actions may be activated only when larger activity is detected, so methods for detecting possible error situations are developed. However, misdetection is not a serious problem because the Kalman correction methods only track significant errors in the data. Two activity detection techniques are examined; one is based on likelihood ratio tests while another uses clipped samples and binary pattern matching. Several examples showing simulated mean-square error performance and decoded waveforms from error injection experiments are presented     

基于FPGA的功能域隔离电路设计

静态随机存储器(Static Random Access Memory, SRAM)型现场可编程门阵列（Field Programmable Gate Array, FPGA）广泛应用于航空航天系统中,但是高空中FPGA易受高能粒子影响造成配置出错,互联资源上发生的单点错误可能导致跨域故障,使芯片内多个模块同时失效。跨域故障可能导致电路中的工作模块与检错模块同时故障,使设备中存在不能被检测到的隐蔽故障。针对上述问题,提出在芯片上将不同功能的模块相互隔离,并通过约束实现模块间可信通信的故障隔离方法,将故障限定在单一模块内,防止多个模块同时失效,提高电路的容错能力。通过故障注入评估隔离设计前后的航空电子全双工交换式以太网（Avionics Full Duplex Switched Ethernet, AFDX）电路的各类故障发生率。实验结果证明隔离设计可以与电路原有的检错容错机制结合,将隐蔽故障的发生率降为原来的3%。     

On Concurrent Detection of Errors in Polynomial Basis Multiplication

The detection of errors in arithmetic operations is an important issue. This paper discusses the detection of multiple-bit errors due to faults in bit-serial and bit-parallel polynomial basis (PB) multipliers over binary extension fields. Our approach is based on multiple parity bits. Experimental results presented here show that due to an increase in the number of parity bits, the area overhead tends to increase linearly, but the probability of error detection approaches unity fairly quickly, e.g., for eight parity bits. In bit-serial implementation of a GF(2¹⁶³) PB multiplier using eight parity bits, the area overhead and the probability of error detection are 10.29% and 0.996, respectively. This is achieved without any increase in the computation time of the GF(2¹⁶³) PB multiplier     

Geometrical Error Modeling and Compensation Using Neural Networks

This paper describes an approach based on neural networks (NNs) for geometrical error modeling and compensation for precision motion systems. A laser interferometer is used to obtain the systematic error measurements of the geometrical errors, based on which an error model may be constructed and, consequently, a model-based compensation may be incorporated in the motion-control system. NNs are used to approximate the components of geometrical errors, thus dispensing with the conventional lookup table. Apart from serving as a more adequate model due to its inherent nonlinear characteristics, the use of NNs also results in less memory requirements to implement the error compensation for a specified precision compared to the use of lookup table. The adequacy and clear benefits of the proposed approach are illustrated via applications to various configurations of precision-positioning stages, including a single-axis, a gantry, and a complete XY stage     

A Regularized LMS Algorithm for Narrowband Interference Rejection in Direct Sequence Spread Spectrum Communications

A regularized LMS technique is presented that uses a modified optimality criterion which enhances the detection capabilities of direct sequence spread spectrum systems. The rejection filter is updated based upon an additional regularization input which limits the self-noise of the filter, especially at moderate signal-to-interference power ratios. The regularization is controlled by a single scalar parameter, that can be varied to produce the optimal Wiener filter weights or the decision-feedback filter weights. An advantage of the regularized filter is that the weight error surface is quadratic, leading to well behaved convergence properties for adaptive implementations. Simulation results are presented which compare the regularized filter to the optimal Wiener filter and the decision-feedback filter.     

基于通道误差校准的空域导向矢量多通道SAR-GMTI 杂波抑制方法

针对通道幅相误差和图像配准误差等非理想因素导致地面动目标检测性能下降的问题,该文结合最小方差和空域导向矢量两种杂波抑制算法,提出一种基于通道误差校准的空域导向矢量杂波抑制方法。该方法首先计算最小方差杂波抑制的权向量,通过该权向量构造配准图像,然后利用配准图像计算杂波正交补空间,最后通过正交子空间的方法实现杂波抑制。理论分析及实验结果表明,所提方法在图像配准误差和通道幅相误差较大的情况下仍具有很好的检测性能,能获得较最小方差杂波抑制方法和基于空域导向矢量的杂波抑制方法更高的信杂噪比。      

Error accumulation effects for the a posteriori RLSL predictionfilter

This paper presents a numerical analysis of the a posteriori recursive least-squares lattice filter with indirect updating. The important problem of finite precision effects in adaptive RLS lattice filters is addressed for this particular filter algorithm but the technique is applicable to many other versions. New recursions for the filter residuals and the filter powers (forward and backward) are derived which describe the effects of arithmetic errors that originate at one stage (m) and are passed to the next stage (m+1). These recursions permit an arithmetic error analysis at the zeroth filter stage to have meaning at all future filter stages. Effects from machine precision, η, are linked to the forgetting factor, λ, and time, n, to derive bounds for arithmetic error growth at the zeroth filter stage. These results provide an explicit upper bound on the forgetting factor that ensures acceptable error propagation. Additionally, we offer a computationally inexpensive way to monitor arithmetic error effects during the normal execution of the filter algorithm through a running error analysis     

The Effects of Equalization, Timing, and Carrier Phase on the Eye Patterns of Class-4 Partial-Response Data Signals

A general expression is derived for the eye pattern boundaries of a multilevel class-4 partial-response (PR) signal after single-sideband amplitude-modulation (SSBAM) transmission with a carrier phase error. From the expression particular results are obtained for the horizontal and vertical eye openings of the signal. Expressions are derived for the tap settings of a linear transversal equalizer using the minimum mean-square error (MMSE) criterion when the class-4 PR signal is distorted by a carrier phase error and sampled with timing error. The values of the tap settings can be used to reduce the carrier and timing phase errors. Finally, an expression for the vertical eye opening of the equalized signal is derived as a function of the carrier phase and the number of stages in the equalizer.     

Unique-Word Detection in TDMA: Acquisition and Retention

Establishing frame and burst synchronism in TDMA requires detection of a known, approximately periodic signal corrupted by noise. This paper presents a Markovian modeling approach to analyzing the performance of a sync detector that repeatedly compares the output of ann-bit binary correlator to an acceptance/rejection threshold. The detector is defined to be in one of two modes of operation: INITIAL ACQUISITION, during which it seeks to identify the start of a frame; and RETENTION, in which periodic detection of the frame (and burst) is essential for TDMA operations. During acquisition, then-bit sync word is assumed embedded in random data, and bit errors are assumed uncorrelated. The acquisition models permit ready computation of acquisition-time statistics and the probability of false acquisition. The retention models identify paths by which synchronism can be lost, their probability of occurrence, and a resulting mean time to loss of synchronism. Unlike the acquisition models, account is taken of the deterministic data pattern immediately preceding the sync word, and sources of timing error that alter the sync word's ideally periodic arrival. The models presented in this paper allow the detector's key performance indexes to be assessed as a function of its external environment: bit-error rate, timing uncertainty, and data pattern preceding the sync word; and internal parameters: sync word pattern, correlation detection threshold, detection aperture widths, number of consecutive detections before acquisition can be declared, and the number of tolerable consecutive sync word misses before synchronism is declared lost.     

基于激光跟踪仪的转台系统几何误差检测

转台系统是多轴机床的基本组件,因此转台系统的几何误差检测对于多轴机床的误差补偿有重要意义。提出了一种基于激光跟踪仪的转台系统几何误差检测方法,利用齐次坐标变换建立转台系统的误差模型,并给出几何误差与空间误差之间的关系。利用激光跟踪仪检测转台上不共线的三个点的空间坐标并得到各点的空间误差,再逆用误差模型,建立了包含六项几何误差的方程组。求解方程组,获得了转台系统的六项几何误差的解析表达式。将检测方法应用于某转台系统的几何误差检测,并通过对比实验证明了该方法的有效性。     

Concurrent Error Detection in Reed–Solomon Encoders and Decoders

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2^m). These properties are related to the parity of the binary representation of the elements of the Galois field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.