A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

Essential Considerations in Implementing the Smart Antenna System for Downlink Beamforming

This paper addresses some essential problems that have to be taken into consideration in implementing the smart antenna base station (SABS) for downlink beamforming. In order to provide proper downlink beamforming as well as uplink beamforming, a pragmatic procedure of automatic calibration is proposed. Through the experimental test, we confirm that the proposed calibration technique has eliminated the problem of the phase differences of the signal path associated with each antenna. Also, in this paper, we first analyze the multipath condition under which the auxiliary pilot becomes indispensable for detecting the data transmitted on the data channel and what happens if the auxiliary pilot is not available. Then, the performance of the downlink beamforming utilizing the auxiliary pilot is analyzed through the computer simulations. Finally, we present a comparison of downlink communications to uplink ones in terms of throughputs available at each of uplink and downlink communications. Weon-Cheol Lee received the B.S, M.S, and Ph.D. degree in Electronic Communication Engineering from Hanyang University, Korea, in 1992, 1994, 2005, respectively. From 1994 to 2000, he was with LG Electronic Inc., where he had worked for developing the digital VCR, digital cable modem, digital TV. Since 2001, he has been a professor with department of information and communications, Yong-in Songdam College, Korea. His research interests include smart antennas, mobile communications beyond the third generation, digital broadcasting technology, and communication signal processing. Dr. Lee also received the Best Research Paper Award and Excellent Research Engineer Award from LG Electronics, respectively. Seungwon Choireceived the BS degree from Hanyang University, Seoul, Korea, and the M.S. degree from Seoul National University, Korea, 1980 and 1982, respectively, both in electronics engineering, the MS degree (computer engineering) in 1985, and the PhD degree (electrical engineering), in 1988, both from Syracuse University, Syracuse, NY. From 1988 to 1989 he was with the Department of Electrical and Computer Engineering of Syracuse University, Syracuse, NY, as an Assistant Professor. In 1989 he joined the Electronics and Telecommunications Research Institute, Daejeon, Korea. From 1990 to 1992 he was with the Communications Research Laboratory, Tokyo, Japan, as a Science and Technology Agency fellow, developing the adaptive antenna array systems and adaptive equalizing filters. He joined Hanyang University, Seoul, Korea, in 1992 as an assistant professor. He is a professor in the School of Electrical and Computer Engineering of Hanyang University. Since 2003, Dr. Choi has been serving as a Vice Chairman and the representative of the ITU region 3 for SDR (Software Defined Radio) Forum and as a Director of the HY-SDR Research Center, MIC, Korea. His research interests include digital communications and adaptive signal processing with a recent focus on the implementation of the smart antenna systems for both mobile communication systems and wireless data systems. Jae-Moung Kim received the BS degree from Hanyang University, Korea in 1974, the MSEE degree from University of Southern California, USA in 1981, and the PhD degree from Yonsei University, Korea in 1987. He was a Vice President of Radio {&} Broadcasting Technology Laboratory and Director of Satellite Communication System Department at Electronics and Telecommunications Research Institute (ETRI) from September 1982 to March 2003. Since April of 2003, he has been a Professor in the Graduate School of Information Technology and Telecommunications, Inha University. He is a board member of directors of Korean Institute of Communication Science (KICS), a Vice President of Korea Society of Broadcast Engineers (KOSBE) and a senior member of IEEE. His research background is telecommunication systems modeling and performance analysis of broadband wireless access systems, mobile communications, satellite communications and broadcasting transmission technologies.     

An Analog Circuit Fault Characterization Methodology

A methodology for diagnosing and characterizing multiple faults in analog circuits, and results from applying this methodology to a real circuit is presented. Our method is a novel combination of a Simulation Before Test (SBT) and Interpolation After Test (IAT) methodology. Our method uses the classical SBT concept of a fault dictionary database constructed before test. It also uses a method of IAT that consists in using the measurements to guide an interpolation algorithm to effectively increase the local resolution of the fault dictionary database and thereby yield the most likely test parameter value. Our methods underlying principle is to characterize the fault-free and faulty circuit cases by their impulse responses obtained by simulation and subsequently stored in a fault dictionary database. The method uses the technique of Lagrange interpolation to resolve the faults between the fault dictionary database entries and the actual measurements. Our experimental results reveal that the method is effective for characterizing faults when the simulations match the measurements sufficiently. Consequently, the methods effectiveness depends highly on the quality of the models used to build the dictionary as well as on the accuracy of the measurements.Yvan Maidon was born in Bordeaux, France. He received the M.Sc degree in (electronics) applied physics from the University of Bordeaux, in 1980. He is currently Head of the Department for Applied Sciences in Electrical and Electronic Engineering at the University of Bordeaux 1. His special research interests include failure analysis and relaibility of analog circuits. He has also developed original BICS for mixed circuits and SoC testing.Thomas Zimmer is currently Professor at the University of Bordeaux 1. He received the M.Sc. degree in physics from the University of Würzburg, Germany, in 1989 and the Ph.D. degree in electronics from the University of Bordeaux 1, France, in 1992. His research interests include characterization and modeling of high frequency bipolar devices. He has authored and co-authored about 70 scientific and technical publications including several book chapters. He is also co-founder of the start-up company XMOD.André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS 02) and the General Chair for VTS 03 and VTS 04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwers Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Societys Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia.     

A low-power sigma-delta modulator for wireless communication receivers using adaptive biasing circuitry and cascaded comparator scheme

This paper represents the low-power signal-delta (ΣΔ) modulator for wireless communication receiver applications. The 2nd-order modulator has a single-loop structure with 11 quantization levels. An adaptive biasing scheme of the operational amplifier and cascaded comparator scheme are proposed in order to save the power consumption. The DAC with three-level references including the analog ground voltage can make the modulator be implemented with half of the input capacitances without degradation of linearity characteristics with the help of dynamic element matching technique. Peak SNR values of 74 dB and 68 dB are achieved with the input bandwidths of 615 kHz and 1.92 MHz for CDMA-2000 and WCDMA applications, respectively. The modulator is fabricated in a 0.13-μm standard digital CMOS technology and dissipates 4.3 mA for a single supply voltage of 2.8 V. Jinup Lim was born in Seoul, Korea, in 1973. He received the B.S. and the M.S. degrees in semiconductor engineering from University of Seoul, Seoul, Korea, in 1999 and 2001, respectively. From 2001 to 2002, he worked in GCT Semiconductor Inc., Seoul, Korea. He is currently working toward the Ph.D. degree in Electrical & Computer Engineering at the same university. He received the Best student paper award from IEEE SSCS/EDS Seoul Chapter in 2004 and the Samsung Best paper award third prize in ISOCC 2004. His research area is the design of high-performance discrete-time / continuous-time sigma-delta modulator circuits. Joongho Choi was born in Seoul, Korea, in 1964. He received the B.S. and the M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1987 and 1989, respectively. In 1993, he received Ph.D. degree in electrical engineering from University of Southern California, CA, USA. From 1994 to 1996, he worked in IBM T. J. Watson Research Center, NY, USA. In 1996, he joined the University of Seoul, Seoul, where he is currently a professor in the Department of Electrical & Computer Engineering. His research area is the design of high-performance analog integrated circuits.     

A Video Streaming System for Mobile Phones: Practice and Experience

This paper presents a case of video streaming system for mobile phone which has actually been implemented and deployed for commercial services in CDMA2000 1X cellular phone networks. As the computing environment and the network connection of cellular phones are significantly different from the wired desktop environment, the traditional desktop streaming method is not applicable. Therefore, a new architecture is required to suit the successfully streaming in the mobile phone environment. We have developed a very lightweight video player for use in mobile phone and the related authoring tool for the player. The streaming server has carefully been designed to provide high efficiency, reliability and scalability. Based on a specifically-designed suite of streaming protocol, the server employs an adaptive rate control mechanism which transmits the media packets appropriately into the network according to the change in network bandwidth.Hojung Cha is currently a professor in computer science at Yonsei University, Seoul, Korea. His research interests include multimedia computing system, multimedia communication networks, wireless and mobile communication systems and embedded system software. He received his B.S. and M.S. in computer engineering from Seoul National University, Korea, in 1985 and 1987, respectively. He received his Ph.D. in computer science from the University of Manchester, England, in 1991.Jongmin Lee is a Ph.D. candidiate in computer science at Yonsei University, Seoul, Korea. His research interests include wireless multimedia system, QoS architecture, multimedia communication networks. He received his B.S. and M.S. in computer science from Kwangwoon University in 1999 and 2001, respectively.Jongho Nang is a professor in the Department of Computer Science at Sogang University. He received his B.S. degree from Sogang University, Korea, in 1986 and M.S. and Ph.D. degree from KAIST, in 1988 and in 1992, respectively. His research interests are in the field of multimedia systems, digital video library, and Internet technologies. He is a member of KISS, ACM, and IEEE.Sung-Yong Park is an associate professor in the Department of Computer Science at Sogang University, Seoul, Korea. He received his B.S. degree in computer science from Sogang University, and both the M.S. and Ph.D. degrees in computer science from Syracuse University. From 1987 to 1992, he worked for LG Electronics, Korea, as a research engineer. From 1998 to 1999, he was a research scientist at Telcordia Technologies (formerly Bellcore) where he developed network management software for optical switches. His research interests include high performance distributed computing and systems, operating systems, and multimedia.Jin-Hwan Jeong received the B.S. and M.S. degrees in computer science from Korea University, Seoul, Korea, in 1997, and 1999, respectively. He is currently in Ph.D. course at Korea University. His research interests include video processing for thin devices, multimedia streaming and operating systems.Chuck Yoo received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea and the M.S. and Ph.D. in computer science in University of Michigan. He worked as a researcher in Sun Microsystems Lab. from 1990 to 1995. He joined the Computer Science and Enginnering Department, Korea University, Seoul, Korea in 1995, where he is currently a professor. His research interests include high performance network, multimedia streaming, and operating systems.Jin-Young Choi received the B.S. degree from Seoul National University, Seoul, Korea, in 1982, the M.S. degree from Drexel University in 1986, and the Ph.D. degree from University of Pennsylvania, in 1993. He is currently a professor of Computer Science and Engineering Department, Korea University, Seoul, Korea. His current research interests are in real-time computing, formal methods, programming languages, process algebras, security, software engineering, and protocol engineering.     

Design of Current-Mode Square-Root Domain Band-Pass Filter with Reduced Voltage

A design technique for current-mode square-root domain band-pass filter fabricated in a 0.25 μ m CMOS process is presented. The basic building block consists of current-mode current mirrors, square-root circuits and capacitors, and in which the overall supply voltage is reduced by adopting low-voltage level-shift current mirror. Both of the simulation and measured results, which are in good agreement, indicate that the prototype of the band-pass provides tunable center frequency of 4–10 MHz with bias-current-tunable, −26.7 dB total harmonic distortion (THD), and approximately 1.598 mW power dissipation with a 1.5 V supply voltage. Advantages of the proposed filter include high frequency operation, tuneability, low supply voltage operation, low power consumption, and low third order intermodulation distortion. Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C. Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000. His current researches include current-mode circuits design, analog IC design and VLSI circuit design. Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design. Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002. Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively. Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordn, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits & Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.     

Cycle-Accurate Energy Measurement and Characterization of FPGAs

Field Programmable Gate Arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip (SoC) designs. Nevertheless, FPGA vendors cannot accurately specify the power consumption of their products on device data sheets because the power consumption of FPGAs is strongly dependent on the target circuit, including resource utilization, logic partitioning, mapping, placement and routing. Although major CAD tools have started to report average power consumption under given transition activities, power-efficient FPGA design demands more detailed information about power consumption. In this paper, we introduce an in-house cycle-accurate FPGA energy measurement tool and energy characterization schemes spanning low-level to high-level design. This tool offers all the capabilities necessary to investigate the energy consumption of FPGAs for operation-based energy characterization, which is applicable to high-level and system-wide energy estimation. It also includes features for low-level energy characterization. We compare our tool with Xilinx XPower and demonstrate the state-machine-based energy characterization of an SDRAM controller.The RIACT at Seoul National University provide research facilities for this study. This work was partly supported by the Brain Korea 21 Project.Hyung Gyu Lee received the B.S. degree in Dept. of Computer Engineering from DongGuk University, in 1999, M.S. degree in School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2001, and is currently working toward the Ph.D. degree at Seoul National University. His research interests include device-level energy measurement and characterization, system-level low power design and low-power FPGA design.KyungSoo Lee is a M.S. student at the School of Computer Science and Engineering, Seoul National University. He received the B.S. degree in the School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2004. He is currently working on low-power systems and embedded systems for his M.S. degree.Yongseok Choi received the B.S. and M.S. degree in the School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2000 and 2002, respectively. He is currently working toward the Ph.D. degree in the School of Computer Science and Engineering at Seoul National University. His research interests include embedded systems and low power systems.Naehyuck Chang received his B.S., M.S. and Ph.D. degrees all from Dept. of Control and Instrumentation Engineering, Seoul National University, Seoul, Korea, in 1989, 1992 and 1996, respectively. Since 1997, he has been with School of Computer Science and Engineering, Seoul National University and currently is an Associate Professor. His research interest includes system-level low-power design and embedded systems design.     

The Coupling Model for Function and Delay Faults

We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function. This research was sponsored in part by the U.S. National Science Foundation under Grants No. CCR-9872066 and CCR-0073406. Joonhwan Yi received the B.S degree in electronics engineering from Yonsei University, Seoul, Korea, in 1991, and the M.S. and Ph.D degrees in electrical engineering and computer science from the University of Michigan, Ann Arbor, in 1998 and 2002, respectively. From 1991 to 1995, he was with Samsung Electronics, Semiconductor Business, Korea, where he was involved in developing application specific integrated circuit cell libraries. In 2000, he was a summer intern with Cisco, Santa Clara, CA, where he worked for path delay fault testing. Since 2003, he has been with Samsung Electronics, Telecommunication Network, Suwon, Korea, where he is working on system-on-a-chip design. His current research interests include C-level system modeling for fast hardware and software co-simulation, system-level power analysis and optimization, behavioral synthesis, and high-level testing. John P. Hayes received the B.E. degree from the National University of Ireland, Dublin, and the M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign, all in electrical engineering. While at the University of Illinois, he participated in the design of the ILLIAC III computer. In 1970 he joined the Operations Research Group at the Shell Benelux Computing Center in The Hague, where he worked on mathematical programming and software development. From 1972 to 1982 he was a faculty member of the Departments of Electrical Engineering– Systems and Computer Science of the University of Southern California, Los Angeles. Since 1982 he has been with the Electrical Engineering and Computer Science Department of the University of Michigan, Ann Arbor, where he holds the Claude E. Shannon Chair in Engineering Science. Professor Hayes was the Founding Director of the University of Michigan's Advanced Computer Architecture Laboratory (ACAL). He has authored over 225 technical papers, several patents, and five books, including Introduction to Digital Logic Design (Addison-Wesley, 1993), and Computer Architecture and Organization, (3rd edition, McGraw-Hill, 1998). He has served as editor of various technical journals, including the Communications of the ACM, the IEEE Transactions on Parallel and Distributed Systems and the Journal of Electronic Testing. Professor Hayes is a fellow of both IEEE and ACM, and a member of Sigma Xi. He received the University of Michigan's Distinguished Faculty Achievement Award in 1999 and the Humboldt Foundation's Research Award in 2004. His current teaching and research interests are in the areas of computer-aided design, verification, and testing; VLSI circuits; fault-tolerant embedded systems; ad-hoc computer networks; and quantum computing.     

Design of Square-Root Domain Filters

In this paper, a square-root domain band-pass filter and biquad filter which are based on the MOSFET square law are proposed. Both of the square-root domain filters operated at 2.5 V supply voltage are constituted by current mirrors, current-mode square-root circuits and capacitors. The circuits presented have been simulated and fabricated using 0.25 m CMOS process. Both of simulation and measured results which are in good agreement indicate that the center frequency f₀ is not only attainable at megahertz frequencies but also tunable electronically. The proposed circuits have the merits of high frequency operation, tuneability, low power supply voltage operation, low third order intermodulation distortion and low total harmonic distortion.Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C.Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000.His current researches include current-mode circuits design, analog IC design and VLSI circuit design.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design.Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively.Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang, Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordón, F. Herrera, and L. Magdalena, Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits {&} Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002.     

DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation

To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations. Seok-Bae Park received the B.S. and M.S. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Ohio State University, Columbus, Ohio. He is currently with Firstpass Technologies, Inc., Dublin, Ohio as a Senior RF and Mixed-Signal Design Engineer. His current interests include low voltage/low power CMOS RF/analog/mixed-signal integrated circuits and systems for wireless communications. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the far east. He is Professor and The Founding Director of the Analog VLSI Lab, The Ohio State University. He advised the work of 40 PhD students and of 85 MS students. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has coedited and coauthored several books including a text on Analog VLSI Signal and Information Processing, McGraw Hill. His last book (2004) is entitled CMOS PLLs and VCOs for 4G Wireless, Springer. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Firstpass Technologies Inc., a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal’s Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada. He is a Fellow of IEEE.     

On-demand diversity wireless relay networks

There has been much recent attention on using wireless relay networks to forward data from mobile nodes to a base station. This network architecture is motivated by performance improvements obtained by leveraging the highest quality links to a base station for data transfer. With the advent of agile radios it is possible to improve the performance of relay networks through intelligent frequency assignments. First, it is beneficial if the links of the relay network are orthogonal with respect to each other so that simultaneous transmission on all links is possible. Second, diversity can be added to hops in the relay network to reduce error rates. In this paper we present algorithms for forming such relay networks dynamically. The formation algorithms support intelligent frequency assignments and diversity setup. Our results show that algorithms that order the sequence in which nodes join a relay network carefully, achieve the highest amount of diversity and hence best performance. This research is supported in part by NSF grant CNS-0508114. JaeSheung Shin received the B.S. and M.S. degree in Computer Science and Engineering from DongGuk University, Korea, in 1991 and 1993, respectively. He is currently working toward the Ph.D. degree in Computer Science and Engineering at the Pennsylvania State University, University Park. He is a research assistant at the Networking and Security Research Center (NSRC). Prior to joining Pennsylvania State University, he was with Electronics and Telecommunications Research Institute (ETRI), Korea, since 1993. He worked on development of 2G and 3G wireless cellular core network elements. His research interests include mobility management and signaling for wireless cellular and routing and resource allocation for multi-radio multi-hop wireless cellular networks. Kyounghwan Lee received the B.S. degree in Electrical and Electronics Engineering from University of Seoul, Seoul, Korea, in 2000, and the M.S. degree in Information and Communication Engineering from Gwangju Institute of Science and Technology, Gwangju, Korea, in 2002. He is currently a Ph.D candidate at the Electrical Engineering department at the Pennsylvania State University and a research assistant at the Wireless Communications and Networking Laboratory (WCAN@PSU). His research interests include wireless communication theory and relay networks. E-mail: kxl251@psu.edu Aylin Yener received the B.S. degrees in Electrical and Electronics Engineering, and in Physics, from Bogazici University, Istanbul, Turkey, in 1991, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Rutgers University, NJ, in 1994 and 2000, respectively. During her Ph.D. studies, she was with Wireless Information Network Laboratory (WINLAB) in the Department of Electrical and Computer Engineering at Rutgers University, NJ. Between fall 2000 and fall 2001, she was with the Electrical Engineering and Computer Science Department at Lehigh University, PA, where she was a P.C. Rossin assistant professor. Currently, she is with the Electrical Engineering department at the Pennsylvania State University, University Park, PA, as an assistant professor. Dr. Yener is a recipient of the NSF CAREER award in 2003. She is an associate editor of the IEEE Transactions on Wireless Communications. Dr. Yener’s research interests include performance enhancement of multiuser systems, wireless communication theory and wireless networking. Thomas F. La Porta received his B.S.E.E. and M.S.E.E. degrees from The Cooper Union, New York, NY, and his Ph.D. degree in Electrical Engineering from Columbia University, New York, NY. He joined the Computer Science and Engineering Department at Penn State in 2002 as a Full Professor. He is the Director of the Networking Research Center at Penn State. Prior to joining Penn State, Dr. La Porta was with Bell Laboratories since 1986. He was the Director of the Mobile Networking Research Department in Bell Laboratories, Lucent Technologies. He is an IEEE Fellow and Bell Labs Fellow. Dr. La Porta was the founding Editor-in-Chief of the IEEE Transactions on Mobile Computing. He has published over 50 technical papers and holds 25 patents.     

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smart-memory coprocessors. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project has built a prototype development system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently ported several demonstration kernels to this platform and have exhibited a speedup of 35X on a matrix transpose operation.This paper focuses on the 32-bit scalar and 256-bit WideWord integer processing components of the first DIVA prototype PIM chip, which was fabricated in TSMC 0.18 m technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little smart logic added to memory devices. A second PIM prototype that includes WideWord floating-point capability is scheduled to tape out in August 2003.Jeffrey Draper is a Research Assistant Professor in the Department of Electrical Engineering at the University of Southern California. He holds this appointment in conjunction with a Project Leader position at the Information Sciences Institute of the University of Southern California. Dr. Drapers research group has participated in many DARPA-sponsored large-scale VLSI development efforts. He is a member of the IEEE Computer Society and has conducted research in the areas of processing-in-memory architectures, thermal management, VLSI, interconnection networks, and modeling/performance evaluation. Dr. Draper received a BSEE from Texas A&M University and an MS and PhD from the University of Texas at Austin.J. Tim Barrett is a Senior Electrical Engineer at the Information Sciences Institute of the University of Southern California. Mr. Barrett has managed, designed and implemented the hardware, low-level software and integration of many computer systems. Applications of these systems include scalable supercomputers at USC Information Sciences Institute, the long distance telephone switch at AT&T Bell Labs, building energy management at Barber-Colman Company, and laser entertainment performance instruments at Aura Technologies and Laser Images Inc. He is a member of IEEE Solid State Circuits Society and received his MSCS from the University of Illinois Chicago and BSEE from the University of Iowa.Jeff Sondeen is a Research Associate at the Information Sciences Institute of the University of Southern California, where he supports and maintains CAD technology files, libraries, and tools for implementing VLSI designs. Previously he has worked at Silicon Compilers and Hewlett-Packard in CAD tool and test chip development. He received an MSEE from the University of Michigan.Sumit Mediratta is currently pursuing a PhD in Electrical Engineering at the University of Southern California. He received a Bachelor of Engineering degree in Electronics and Telecommunication from the Shri Govind Ram Sekseria Institute of Technology and Science, India. His research interests include interconnection networks, VLSI, processing-in-memory architectures, high-speed data communication and synchronization techniques and network interfaces for high-performance architectures.Chang Woo Kang received a BS in electrical engineering from Chung-ang University, Seoul, South Korea, in 1997 and an MS in electrical engineering from the University of Southern California, Los Angeles, in 1999. He is currently pursuing a PhD in electrical engineering at the University of Southern California. His research includes VLSI system design and algorithms for low-power logic synthesis and physical design.Ihn Kim is a PhD student in the Department of Electrical Engineering at the University of Southern California. He is also a Staff Engineer at QLogic. His research interests include user-level network interface, network processor architectures, and modeling/performance evaluation of system area networks. He is a member of the IEEE Computer Society. He received an MS at KAIST (Korea Advanced Institute of Science and Technology).Gokhan Daglikoca is an Application Engineer at Cadence Design Systems, Inc, where he specializes in High-Performance ASIC and Microprocessor Design Methodologies. He is a member of IEEE. Gokhan Daglikoca received a BS from Istanbul Technical University and an MS from the University of Southern California.     

A Hybrid Error Recovery scheme for Scalable Video Transmission over 3G Cellular Broadcast Networks

The cdma2000 1xEV-DO mobile communication system provides broadcast and multicast services (BCMCS) to meet an increasing demand for multimedia data services. But the servicing of video streams over a BCMCS network faces a challenge from the unreliable and error-prone nature of the radio channel. BCMCS uses Reed-Solomon coding integrated with the MAC protocol for error recovery. We show that this is not effective for mobiles moving at the edge of service area, where the channel condition is bad, resulting in significantly lower video quality. To improve the playback quality of an MPEG-4 FGS (fine granularity scalability) video stream, we propose a hybrid error recovery scheme incorporating a packet scheduler, which uses slots saved by reducing the Reed-Solomon coding overhead. Packets to be retransmitted are prioritized by a utility function which reduces the packet error-rate in the application layer within a fixed retransmission budget by considering of the map of the error control block at each mobile node. Our error recovery scheme also uses the characteristics of MPEG-4 FGS to improve the video quality even for a slow-moving mobile which is experiencing a high error-rate in the physical channel because of error bursts. Kyungtae Kang received B.S. (1999) and M.S. (2001) degrees in computer engineering from Seoul National University, Korea. He received Ph.D. degree in Dept. of Electrical Engineering and Computer Science from Seoul National University, Korea in 2007. He is a member of IEEE and IEICE. His research interests include packet scheduling, error control, QoS provision, and energy minimization issues in nextgeneration wireless/mobile networks. In particular, he is researching the performance and energy requirements of 3G cellular broadcast services such as BCMCS and MBMS. Yongwoo Cho received the Premedical Degree from the College of Medicine, University of Ulsan, in 1997, a B.S. degree in Computer Science from Korea National Open University in 2004, while he was an military service, and an M.S. degree in Electrical Engineering and Computer Science from Seoul National University in 2006. He has worked as a researcher in Dooin Corp. and as a general manager in Bluecord Technology, Inc. His primary interests include multimedia systems, digital broadcasting, next-generation wireless/mobile networks, error control, real-time computing, and low-power design. He is currently a Ph.D. student in the School of Electrical Engineering and Computer Science at Seoul National University. Heonshik Shin received the B.S. degree in applied physics from Seoul National University, Korea, in 1973. Since he received Ph.D. degree in computer engineering from the University of Texas at Austin in 1985, he has actively involved himself in researches of various topics, ranging from real-time computing and distributed computing to mobile systems and software. He is currently a professor of School of Computer Science and Engineering at Seoul National University.     

On Downlink Beamforming Methods: Capacity and Error Probability Performance

In space-division multiple access (SDMA), different beamforming or space-domain precoding techniques can be applied. We investigate two different space-domain precoding methods, the maximum capacity (MC) and the minimum mean square error (MMSE) precoders, for the downlink channel. It is shown that the MMSE precoding, which is practically implementable, can provide a reasonable performance in terms of the capacity and error probability, while the MC precoding is not practical (although it is optimum in terms of the capacity). Space-domain precoding methods are also applied to code-division multiple access (CDMA) systems.This work was supported by the HY-SDR Research Center at Hanyang University, Seoul, Korea, under the ITRC Program of MIC, Korea.Jinho Choi was born in Seoul, Korea. He recieved the B.E. degree (magna cum laude) in electronics engineering from Sogang University in 1989 and the M.S.E. and Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology in 1991 and 1994, respectively. Currently he is a Senior Lecturer in the School of Electrical Engineering and Telecommunications,University of New South Wales, Australia. Dr. Choi received the 1999 Best Paper Award of Signal Processing from EURASIP.Seungwon Choi received the B.S. degree from Hanyang University, Seoul, Korea, in 1980 and the M.S. degree from Seoul National University, Seoul, in 1982, both the electronic engineering. He received the M.S. degree in computer engineering in 1985 and the Ph.D degree in electrical engineering in 1988 from Syracuse University, Syracuse, NY.From 1982 to 1984, he was with LG Electronics Co. Ltd., Seoul, where he helped developed the 8-mm camcorder system. From 1988 to 1989, he was with the Department of Electrical and Computer Engineering, Syracuse University, as an Assistant Professor. In 1989, he joined the Electronics and Telecommunications Research Institute, daejeon, Korea, where he developed the adaptive algorithm for real-time application in secure telephone systems. From 1990 to 1992, he was with yhe Communication Research Laboratory, Tokyo, Japan, as a science and Technology Agency Fellow, developing adaptive antenna array system and adaptive equalizing filters for applications in land-mobile communications. He joined Hanyang University, Seoul, in 1992 as an Assistant Professor. He is a Professor in the School of Electrical and Computer Engineering, Hanyang University. His research interests include digital communications and adaptive signal processing with a recent focus on the real-time implementation of smart antenna system for 3G mobile communication system.     

Implementation of a Wireless Multimedia DSP Chip for Mobile Applications

This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perform four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 m HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.Junghoo Lee received the B.S. degree in electronic engineering from Ajou University, Suwon, Korea in 2002. He is currently working toward the Ph.D. degree with School of Electrical and Computer Engineering, Ajou University. His main research interests include SOC design and application-specific DSP chip design.Myung H. Sunwoo received the B.S. degree in electronic engineering from the Sogang University in 1980, the M.S. degree in electrical and electronics from the Korea Advanced Institute of Science and Technology in 1982, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin in 1990.He worked for Electronics and Telecommunications Research Institute (ETRI) in Daejeon, Korea from 1982 to 1985 and Digital Signal Processor Operations, Motorola, Austin, TX from 1990 to 1992. Since 1992, he has been a Professor with the School of Electrical and Computer Engineering, Ajou University in Suwon, Korea. In 2000, he was a Visiting Professor in the Department of Electrical and Computer Engineering, the University of California, Davis, CA. He is the Director of the National Research Laboratory sponsored by the Ministry of Science and Technology. His research interests include VLSI architectures, SOC design for multimedia and communications, and application-specific DSP architectures.Dr. Sunwoo has published more than 120 papers in international transactions/journals and conferences and also has 28 patents including five U.S. patents. He served as a Technical Program Chair of the IEEE Workshop on Signal Processing Systems (SIPS) in 2003 and a member of the technical program committee of various international conferences. He has received a number of research awards from the Ministry of Commerce, Industry and Energy, Samsung Electronics, and professional foundations. He served as an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002–2003) and as a Guest Editor for the Journal of VLSI Signal Processing (Kluwer, 2004). Currently, He is a Senior Member of IEEE and a Chair of the IEEE CAS Society of the Seoul Chapter.     

Effective Paging Strategy based on Location Probability of Mobile Station and Paging Load Distribution of Base Station in Mobile Communication Networks

When the cells in a location area are sequentially paged based on specific information, such as the last registered area or a mobile speed, the paging load may be non-uniformly distributed among the cells. This non-uniform paging traffic causes an additional paging delay due to the increased waiting time in cells that have a high paging load. In this paper, we introduce a new paging strategy in which the paging sequence in a location area is optimized according to both the location probability of a mobile terminal and the paging load distribution among the cells. In addition, we propose a simple polynomial-time heuristic algorithm to determine sub-optimal paging sequence. Numerical results show that our proposed strategy has almost an equivalent optimal performance and outperforms the conventional paging scheme with respect to a paging delay. Dong-Jun Lee received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1994, 1996, and 2000, respectively. Since 2000 to 2004, he was with Samsung Electronics Co., Ltd., Korea and participated in developing cdma2000 systems. Since 2005, he has been with Hankuk Aviation University, where he is a professor with School of Electronics, Telecommunications and Computer Engineering. His research interests include radio resource management and location management of 3G and 4G wireless systems. HyeJeong Lee has received the B.S. and M.S. degrees, both in Electrical and Electronics Engineering from the Korea Advanced Institute of Science and Technology (KAIST), in 2000 and 2002, respectively. She is currently working toward the Ph. D. degree in Electrical Engineering at the KAIST. Her current research interests include mobility and resource management and reverse link performance in the high data rate mobile communication networks. Dong-Ho Cho received the B.S. degree in Electrical Engineering from the Seoul National University in 1979, and the M.S. and Ph.D. degrees, both in Electrical and Electronics Engineering from the Korea Advanced Institute of Science and Technology (KAIST), in 1981 and 1985, respectively. From 1987 to 1997, he was Professor of Computer Engineering at the Kyunghee University. Since 1998, he has been Professor of Electrical Engineering at KAIST. He is active as a Technical Program Committee and Chair of several conferences, and a reviewer for IEEE journals. He is a Technical Program Committee of the IEEE WCNC 2005 and Globecom 2005. His research interests include 3G/4G wireless communication network, protocol and services.     

Interactive Content-aware Video Streaming System with Fine Granularity Scalability

Video streaming with varying transmission bandwidth is becoming increasingly important. In this paper, an interactive video streaming system is proposed. Fine Granularity Scalability (FGS) is applied to be the streaming video format. The computational complexity of FGS coding is analyzed to explore an efficient FGS implementation. A new transmission model is proposed for the realization of a content-aware video streaming. At encoder side, the current MPEG-4 FGS coding flow is reordered such that the picture-level maximum can be acquired in advance and bit-plane data can be dynamically adapted. With these proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to achieve a cost-effective solution to FGS implementation. The streaming server can adaptively decide quality-enhanced region by selective enhancement according to both object information from encoding side and user-defined region from receiver side. From the simulation results, it’s demonstrated that the proposed approach can provide better quality in users’ interest regions with no bit-rate or complexity overhead. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S., M.S., and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998, 2000, and 2005, respectively. He serves as senior engineer in SoC Solutions Dept., Vivotek Inc. now. His research interests include video coding algorithms and VLSI architectures for image/video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia coding standard and digital consumer devices. His research interests include video coding, video processing and VLSI design. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics and Optoelectronics Research Laboratories in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Platform-Based MPEG-4 SOC Design for Video Communications

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981-1986), and an Associate Professor (1986-1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT & T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001--2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.