Predicting the process induced warpage of electronic packages using the P–V–T–C equation and the Taguchi method

A critical issue in the manufacturing of electronic packages is the warpage induced during the molding process as a result of differences in the shrinkage of the constituent materials. Package warpage causes serious problems such as the quality degradation of devices and yield loss in manufacturing processes. Loss of lead coplanarity happens due to package warpage and causes difficulty in device testing and surface mount assembly. Internal stresses associated with package warpage can also cause device failures such as die cracking, broken circuits and package cracking.Warpage in IC package has drawn intensive attention in the past. Although the effects of thermal shrinkage were extensively investigated in the literatures, the influence of the cure shrinkage on package warpage had received less attention. Accordingly, this study develops a numerical approach for generating more accurate predictions of the package warpage by taking the effects of both thermal shrinkage and cure shrinkage into account. A three-dimensional finite element model of the small outline package (TSOP) DBS-27P is constructed and the proposed numerical approach, which is based on the P–V–T–C (pressure–volume–temperature–conversion) equation and the CTEs (coefficients of thermal expansion) of the package materials, is employed to predict the warpage at each of its corners under various packaging processing conditions. Using the Taguchi method, the relative influences of the transfer pressure, the packing pressure, the mold temperature and the curing time on the degree of package warpage are identified and the optimal processing conditions are established. A series of experimental packaging trials are performed using the optimal processing conditions. It is found that the warpage of the actual package is in good agreement with that predicted numerically. Therefore, the accuracy of the proposed numerical approach is confirmed. Moreover, the results also demonstrate the capability of the Taguchi method to identify the optimal packaging processing parameters on the basis of a limited number of simulation runs.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

A function-fit model for the hard breakdown I–V characteristics of ultra-thin oxides in MOS structures

A function-fit model for the hard breakdown current–voltage characteristics of ultra-thin oxides in metal–oxide–semiconductor structures based on the smoothing function concept is presented. The model is intended to capture the diode-like and resistance-like behaviours observed at low and high applied biases, respectively, by means of a simple, continuous and derivable function. These features make the proposed expression suited for circuit simulation environments. The effect of temperature on the model parameters is also analysed.     

The effect of small-signal AC voltages on C–V characterization and parameter extraction of SiO2 thin films

The effect of different small-signal ac voltage amplitudes on C–V curves characterized by thin SiO₂ based p-type MOS capacitor with aluminum gate is reported. When the small-signal ac voltage is comparable to the gate bias, the thickness of SiO₂ thin films extracted from the accumulation capacitance is found to be independent of small-signal ac voltage amplitudes, but the flat band voltage shift and interface state density associated with the variation of depletion layer capacitance are dependent on small-signal ac voltage amplitudes. They all increase with the small-signal ac voltage amplitudes. The experimental results reveal that the optimum small-signal ac voltage should be less than 100 mV. The mechanisms involving the depletion layer changes with small-signal ac voltages in SiO₂ thin films are also discussed in this paper.     

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

In this work, charge trapping in SiO₂/Al₂O₃ dielectric stacks is characterized by means of pulsed capacitance–voltage measurements. The proposed technique strongly reduces the measurement time and, as a consequence, the impact of charge trapping on the measurement results. Flat band voltage shift and fast current transient during short stress pulses are systematically monitored and the centroid and the amount of the trapped charge are extracted using a first-order model.     

Analytic expression for the Fowler–Nordheim V–I characteristic including the series resistance effect

It is shown in this communication that the Fowler-Nordheim (FN) tunneling expression for the current-voltage (I-V) characteristic can be analytically inverted so that an exact expression for the voltage-current (V-I) characteristic can be obtained. The solution of the resulting implicit equation is found using the Lambert W function, i.e. the solution of the transcendental equation we^w = x. The reported expressions are supported by experimental I-V curves measured in thin (≈5 nm) SiO₂ films in MOS capacitors. The analysis includes the case of a tunneling oxide with a large series resistance. For practical purposes, a closed-form expression for W based on a Padé-type approximation is also provided.     

Analysis of I–V measurements on PtSi-Si Schottky structures in a wide temperature range

I–V Measurements on PtSi-Si Schottky structures in a wide temperature range from 90 to 350 K were carried out. The contributions of thermionic-emission current and various other current-transport mechanisms were assumed when evaluating the Schottky barrier height Φ₀. Thus the generation-recombination, tunneling and leak currents caused by inhomogeneities and defects at the metal-semiconductor interface were taken into account.

Taking the above-mentioned mechanisms and their temperature dependence into consideration in the Schottky diode model, an outstanding agreement between theory and experiment was achieved in a wide temperature range.

Excluding the secondary current-transport mechanisms from the total current, a more exact value of the thermionic-emission saturation current I_te and thus a more accurate value ofΦ_b was reached.

The barrier height Φ_b and the modified Richardson constant A^** were calculated from the plot of thermionic-emission saturation current I_te as a function of temperature too. The proposed method of finding Φ_b is independent of the exact values of the metal-semiconductor contact area A and of the modified Richardson constant A^**. This fact can be used for determination of Φ_b in new Schottky structures based on multicomponent semiconductor materials.

Using the experimentally evaluated value A^** = 1.796 × 10⁶ Am⁻²K⁻² for the barrier height determination from I–V characteristics the value of Φ_b = 0.881 ± 0.002 eV was reached independent of temperature.

The more exact value of barrier height Φ_b is a relevant input parameter for Schottky diode computer-aided modeling and simulation, which provided a closer correlation between the experimental and theoretical characteristics.     

Study of the electrical cycling stressed large area Schottky diodes using I–V and noise measurements

Large area commercial Al/n-Si Schottky diodes were subjected to an electrical cycling stress in order to cause degradation of diodes with local contact irregularities. Using the I–V characteristics and noise measurements in the frequency range of 10 Hz to 10 kHz at room temperature and using the corresponding equivalent circuit representation of degraded diodes, it has been shown that the latent leakage paths contribute to the degradation of the Schottky diodes under the test conditions. The results could be used to confirm that the ideality factor cannot be alone used as prediction tool of diode behavior under electrical cycling stress. The conclusion of this paper is that the results show that this kind of the stress test can be used as a screening test for diodes with latent leakage current paths.     

Simulation and experimental results on the forward J–V characteristic of Al implanted 4H–SiC p–i–n diodes

In this work the forward J–V characteristics of 4H–SiC p–i–n diodes are analysed by means of a physics based device simulator tuned by comparison to experimental results. The circular devices have a diameter of 350 μm. The implanted anode region showed a plateau aluminium concentration of 6×10¹⁹ cm⁻³ located at the surface with a profile edge located at 0.2 μm and a profile tail crossing the n-type epilayer doping at 1.35 μm. Al atom ionization efficiency was carefully taken into account during the simulations. The final devices showed good rectifying properties and at room temperature a diode current density close to 370 A/cm² could be measured at 5 V. The simulation results were in good agreement with the experimental data taken at temperatures up to about 523 K in the whole explored current range extending over nine orders of magnitude. Simulations also allowed to estimate the effect of a different p⁺ doping electrically effective profile on the device current handling capabilities.     

Impact of the electron, proton and helium irradiation on the forward I–V characteristics of high-power P–i–N diode

2.5 kV/100 A high-power P–i–N diode was electron, proton and helium irradiated in a wide range of irradiation doses with irradiation energies in the MeV range. The resulting forward I–V curves were registered in the temperature range 30–125 °C to investigate the magnitude of the crossing point current of the I–V curves––I_XING. I_XING was found to decrease with increasing irradiation dose and to disappear at high doses for all three irradiation treatments with exception of ion irradiated diodes with defect peaks placed deeply into the anode region. Using a simple model based on the thermal and injection dependence of the carrier lifetime, the explanation of this effect is presented with the support of the non-isothermal 2-D device simulation of helium irradiated devices.     

An accurate mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs with single-channel boron implantation

In this paper we develop an analytical mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs, in which the effects of the two-dimensional electric fields in the surface inversion channel and the parasitic resistances due to contact and interconnection are included. Most importantly, the developed mobility model easily takes the device structure and process into consideration. In order to demonstrate the capabilities of the developed model, the structure- and process-oriented parameters in the present mobility model are calculated explicitly for an n-channel enhancement-mode MOSFET with single-channel boron implantation. Moreover, n-channel MOSFETs with different channel lengths fabricated in a production line by using a set of test keys have been characterized and the measured mobilities have been compared to the model. Excellent agreement has been obtained for all ranges of the fabricated channel lengths, which strongly support the accuracy of the model.     

Prediction of dielectric reliability from I–V characteristics: Poole–Frenkel conduction mechanism leading to √E model for silicon nitride MIM capacitor

Two assumptions lead to a correlation between the leakage mechanism of a dielectric and dielectric reliability: the degradation of the dielectric is a direct cause of the leakage current flowing through the dielectric and breakdown occurs after a critical charge has been forced through the dielectric. The field and temperature dependence of the leakage current mechanism then determine the voltage acceleration factor and the activation energy of TDDB experiments. This simple physical model describes the reliability of metal insulator metal (MIM) capacitors with PECVD SiN remarkably well. The current conduction mechanism is described by Poole–Frenkel theory, leading to a √E dependence of the time to breakdown on the applied electric field. The model predicts correctly the voltage acceleration factor and its temperature dependence and the activation energy.     

Determination of the dice forward I–V characteristics of a power diode from a packaged device and its applications

The forward voltage drop (V_F) of a power diode is an important electrical parameter for a power diode. Diode with excessive V_F can be due to either defects in wafer fabrication or soldering processes. To identify if the defects in soldering process is the root cause to excessive V_F, the obvious method will be the method to extract the series resistance from the diode. However, the present series resistance extraction methods are either inaccurate or requires extensive computation time, and they are not practical for failure analysis and process monitoring. In this work, a modified series resistance extraction method is developed. Experimental results showed that the modified method is accurate, and the computation time is short.     

Improved analysis of pulsed C-t measurements on silicon MOS capacitors

A modified analysis of the pulse response of silicon MOS capacitors is presented which takes into account the lateral spreading of the depletion region around the gate area. Two aspects of this lateral depletion region which have previously been ignored, namely the bulk generation and space charge in this region, are taken into account and used to explain the experimentally observed dependence of the capacitor relaxation time on the device aspect ratio. The analysis allows the bulk lifetime to be obtained more accurately and also enables the surface recombination velocity resulting from a particular device processing schedule to be estimated. The results obtained agree well with those determined from junction leakage current measurements and the relevance of the lateral edge effect to the characteristics of a more complex charge coupled device has been discussed.     

The stability of the CuInSe2 solar mini-module I–V characteristics under continuous and light/dark irradiation cycle tests

The stability of a CIS solar mini-module during a light/dark cycle and continuous light irradiation was investigated. Under both test conditions, the maximum power was improved during the early stages, then subsequently deteriorated. The major factors causing this phenomenon were changes in the fill-factor and open circuit voltage. The details of some parameters relevant to these factors are considered herein. In addition, the dependencies of light intensity and temperature in terms of the I–V characteristics were measured.     

Current reversals in p−n−p transistors

p−n−p silicon bipolar junction transistors (BJTs) have received a greater attention recently in light of the emerging dilemma of performance and power requirements for bipolar VLSI. The current reversal phenomena due to the avalanche breakdown have been the focus of the study of advanced Si p−n−p BJTs in the past. However, a thorough study of current reversals in p−n−p transistors has not been presented yet. In this paper, we study the base and collector current reversals in the inverse mode and their associated physical mechanisms. The collector and base current reversals have been found when the device is operated with or without avalanche effect. Physical mechanisms have been proposed to interpret these phenomena.     

Simulation and analysis of amorphous silicon image sensor having a p−i−n structure

The current-voltage characteristics of a p−i−n a-Si : H contact image sensor under dark and illuminated conditions have been simulated by solving the Poisson's equation and the continuity equations, and the results are correlated with the experiments. The dependence of the dark and photo-currents on the parameters such as the density of states in the gap, intrinsic layer width, dopant concentrations of p⁺ layer and n⁺ layer are discussed.     

Anomalous I–V and pulse noise in reverse biased p–n junctions

A correlation between anomalous I-V characteristics and pulse noise in degraded p-n junctions under reverse bias conditions is found. In order to explain the appearance of two-polarity and multi-level pulse noise, a physical model of noise sources is proposed. The model is based on the presumptions that conduction channels and a p-inversion layer exist in degraded p-n junctions and that the current flow through the defects is modulated by traps adjacent to the defects. The experimental results for silicon field plated PIN photodiodes are in qualitative agreement with the model.     

Some pitfalls in fast ramp C-V measurements

The triangular voltage sweep or fast ramp C-V method, while leading to an easy measurement of deep depletion C-V curves, may have pitfalls for the unwary, particularly in the case of degraded oxides. Two examples of the difficulties associated with the measurement in the presence of positive oxide charge, viz., (i) a distorted fast ramp C-V curve at intermediate bias values and; (ii) a “peak” in the curve due to an inversion layer surrounding the device, are illustrated and explained.