用于倒装芯片的金球凸点制作技术

倒装芯片中凸点用于实现芯片和基板的电路互连,芯片凸点的制作是倒装芯片技术的关键技术之一.对金球凸点制作进行了介绍.金球凸点直接粘附于芯片上,同时又可具有电路互连的作用,可以完成倒装芯片与基板的电气连接.金球凸点的优势是简单、灵活、便捷、低成本,最大特点是无需凸点下金属层(UBM),可对任意大小的单个芯片进行凸点制作,平整度可达到±4μm.     

圆片级封装及带凸点倒装芯片简介

介绍了圆片级封装的定义、状况及支撑技术。     

倒装芯片封装技术的凸点、压焊及下填充

简要叙述了IBM公司的倒装片技术,包括凸点形成技术、压焊技术和下填充技术,并展望了倒装片技术的发展前景.     

倒装芯片凸点制作方法

倒装芯片技术正得到广泛应用，凸点形成是其工艺过程的关键。介绍了现有的凸点制作方法，包括蒸发沉积、印刷、电镀、微球法、黏点转移法、SB2－Jet法、金属液滴喷射法等。每种方法都各有其优缺点，适用于不同的工艺要求。可以看到要使倒装芯片技术得到更广泛的应用，选择合适的凸点制作方法是极为重要的。     

倒装芯片互连凸点电迁移的研究进展

电子产品向便携化、小型化、高性能方向发展,促使集成电路的集成度不断提高,体积不断缩小,采用倒装芯片互连的凸点直径和间距进一步减小和凸点中电流密度的进一步提高,由此出现电迁移失效引起的可靠性问题.本文回顾了倒装芯片互连凸点电迁移失效的研究进展,论述了电流聚集和焊料合金成分对凸点电迁移失效的影响,指出了倒装芯片互连凸点电迁移研究亟待解决的问题.     

技术评论:倒装芯片非焊料高分子凸点工艺

在半导体工业奋力的去迎接明日的封装需求挑战之际,倒装芯片技术无疑将扮演一个重要的角色。为了达到更高的可靠性、更低的成本以及在更小尺寸的封装空间里进行更密集的装配以及更高速度的混合电路的回路,传统的芯片-金线连接方式必须改为倒装芯片的连接技术。倒装芯片封装有以下优点:●更小的尺寸和重量●简化工艺过程并降低构建体系成本●通过缩短信号通道提高电性能●提高散热性能●提高单片电子回路上I/O的数量达到更高的密集度●赋予可使用外围设备或在设计环节里进行排列连接点图案的能力虽然倒装芯片连接在整个连接制造工艺中只占一…     

倒装芯片及封装技术

介绍了倒装芯片的发展过程，其中主要对制造技术、封装方法及倒装焊焊点的可靠性进行了评述。     

应用于倒装芯片的铜钉头凸点技术

铜钉头凸点技术可以为中低I／O密度的器件提供成本最低的倒装芯片封装。     

对Cu焊区的倒装芯片凸点下金属化系统的研究

本文研究了采用化学镀铜（E-Cu）和化学镀镍（E-Ni)方法制作的Cu焊区上倒装芯片焊料凸点用的UBM材料系统，还研究了UBM与Sn-36Pb-2Ag焊料之间的界面反应对焊料凸点连接可靠性的影响，以优化Cu焊区上倒装芯片用的UBM材料。对于E-CuUBM来说，在焊料/E-Cu界面上形成贝壳状的Cu6Sn5金属互化物（IMC），在较小的载荷下沿这个界面发生凸点断裂。与此相反，在E-Nie-Cu UBM的情况下，E-Ni成为一个好的扩散阻挡层。E-Ni有效地限制了IMC在该界面上的生长，而多边形形状的Ni3Sn4IMC产生比E-CuUBM高的附着强度。因此，化学镀沉积的UBM系统被成功地证明可作为低成本的Cu焊区上UBM方法。发现E-NiE-CuUBM材料是比E-Cu UBM更好的Cu焊区上倒装芯片焊料互连的材料。     

倒装焊中复合SnPb焊点形态模拟

本文给出了倒装焊(flip-chip)焊点形态的能量控制方程,采用Surface Evolver软件模拟了倒装焊复合SnPb焊点(高Pb焊料凸点,共晶SnPb焊料焊点)的三维形态.利用焊点形态模拟的数据,分析了芯片和基板之间SnPb焊点的高度与焊点设计和焊接工艺参数的关系.研究表明:共晶SnPb焊料量存在临界值,当共晶SnPb焊料量小于临界值时,焊点的高度等于芯片上高Pb焊料凸点的半径值;当共晶SnPb焊料量大于临界值时,焊点的高度随共晶SnPb焊料量的增加而增加.另外,采用无量纲的形式给出了焊点高度与共晶焊料量、焊盘尺寸、芯片凸点的尺寸,芯片重量之间的关系模型,研究结果对倒装焊焊点形态的控制、工艺参数的优化和提高焊点可靠性具有指导意义.     

Stability of Flip-Chip Interconnects Assembled with Al/Ni(V)/Cu-UBM and Eutectic Pb-Sn Solder During Exposure to High-Temperature Storage

The thermal stability of flip-chip solder joints made with trilayer Al/Ni(V)/Cu underbump metalization (UBM) and eutectic Pb-Sn solder connected to substrates with either electroless Ni(P)-immersion gold (ENIG) or Pb-Sn solder on Cu pad (Cu-SOP) surface finish was determined. The ENIG devices degraded more than 50 times faster than the Cu-SOP devices. Microstructural characterization of these joints using scanning and transmission electron microscopy and ion beam microscopy showed that electrical degradation of the ENIG devices was a direct result of the conversion of the as-deposited Ni(V) barrier UBM layer into a porous fine-grained V₃Sn-intermetallic compound (IMC). This conversion was driven by the Au layer in the ENIG surface finish. No such conversion was observed for the devices assembled on Cu-SOP surface finish substrates. A resistance degradation model is proposed. The model captures changes from a combination of phenomena including increased (1) intrinsic resistivity, (2) porosity, and (3) electron scattering at grain boundaries and surfaces. Finally, the results from this study were compared with results found in a number of published electromigration studies. This comparison indicates that degradation during current stressing in the Pb-Sn bump/ENIG system is in part due to current-crowding-induced Joule heating and the thermal gradients that result from localized Joule heating.     

A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates

The Cu/SnAg double-bump structure is a promising candidate for fine-pitch flip-chip applications. In this study, the interfacial reactions of Cu (60 μm)/SnAg (20 μm) double-bump flip chip assemblies with a 100 μm pitch were investigated. Two types of thermal treatments, multiple reflows and thermal aging, were performed to evaluate the thermal reliability of Cu/SnAg flip-chip assemblies on organic printed circuit boards (PCBs). After these thermal treatments, the resulting intermetallic compounds (IMCs) were identified with scanning electron microscopy (SEM), and the contact resistance was measured using a daisy-chain and a four-point Kelvin structure. Several types of intermetallic compounds form at the Cu column/SnAg solder interface and the SnAg solder/Ni pad interface. In the case of flip-chip samples reflowed at 250°C and 280°C, Cu₆Sn₅ and (Cu, Ni)₆Sn₅ IMCs were found at the Cu/SnAg and SnAg/Ni interfaces, respectively. In addition, an abnormal Ag₃Sn phase was detected inside the SnAg solder. However, no changes were found in the electrical contact resistance in spite of severe IMC formation in the SnAg solder after five reflows. In thermally aged flip-chip samples, Cu₆Sn₅ and Cu₃Sn IMCs were found at the Cu/SnAg interface, and (Cu, Ni)₆Sn₅ IMCs were found at the SnAg/Ni interface. However, Ag₃Sn IMCs were not observed, even for longer aging times and higher temperatures. The growth of Cu₃Sn IMCs at the Cu/SnAg interface was found to lead to the formation of Kirkendall voids inside the Cu₃Sn IMCs and linked voids within the Cu₃Sn/Cu column interfaces. These voids became more evident when the aging time and temperature increased. The contact resistance was found to be nearly unchanged after 2000 h at 125°C, but increases slightly at 150°C, and a number of Cu/SnAg joints failed after 2000 h. This failure was caused by a reduction in the contact area due to the formation of Kirkendall and linked voids at the Cu column/Cu₃Sn IMC interface.     

倒装芯片集成电力电子模块的热设计

将倒装芯片(Flip Chip, FC)技术引入三维集成电力电子模块(Integrated Power Electronic Module,IPEM)的封装,可构建FC-IPEM.在实验室完成了由两只球栅阵列芯片尺寸封装MOSFET和驱动、保护等电路构成的半桥FC-IPEM.针对半桥FC-IPEM,建立半桥FC-IPEM的一维热阻模型,分析模块主要的热阻来源.运用FLOTHERM软件进行三维仿真,得到模块温度分布结果,给出优化模块热性能的依据.     

倒扣芯片连接焊点的热疲劳失效

测量了有无芯下填料B型和D型两种倒扣芯片连接器件的焊点温度循环寿命,运用超声显微镜(C-SAM)和扫描电镜(SEM)观察了焊点微结构粗化和裂纹扩展,并采用三维有限元模拟方法分析了焊点在温度循环条件下的应力应变行为.结合实验和模拟结果,建立了预估焊点疲劳寿命的Coffin-Manson半经验方程,得到方程中的系数C＝5.54,β=-1.38.模拟给出的焊点中剪切应变的轴向分布与实验得到的焊点在温度循环过程中的微结构粗化一致.填充芯下填料后的倒扣芯片连接由于胶的机械耦合作用,降低了焊点的剪切变形,但热失配引起的器件整体弯曲增强,芯片的界面应力增大.模拟结果与实验观察完全一致.     

Evolution of Contact Resistance during the Bonding Process of NCA Flip-Chip Interconnections

Non-conductive adhesive (NCA) flip-chip interconnects are emerging as an attractive alternative to lead or lead-free solder interconnects due to their environmental friendliness, lower processing temperatures, and extendability to fine-pitch applications. The electrical connectivity of an NCA interconnect relies solely on the pure mechanical contact between the integrated circuit (IC) bump and the substrate pad; the electrical conductivity of the contact depends on the mechanical contact pressure, which in turns depends to a large extent on the cure shrinkage characteristics of the NCA. Therefore, it is necessary to monitor the evolution of the electrical conductivity which could reflect the impact of cure- and thermal-induced stresses during the curing and cooling process, respectively. In this article, in situ measurement of the development of contact resistance during the bonding process of test chips was developed by using a mechanical tester combined with a four-wire resistance measurement system. A drop of resistance induced by the cure stress during the bonding process is clearly observed. With decreasing bonding temperature, the drop of contact resistance induced by cure shrinkage becomes larger, while the cooling-induced drop of resistance becomes smaller. The evolution of contact resistance agrees well with experimental observations of cure stress build-up. It is found that vitrification transformation during the curing of the adhesive could lead to a large cure stress and result in the reduction of the␣contact resistance. Furthermore, no obvious changes were observed when the applied load was removed at the end of bonding.     

Characterization of nonconductive adhesives for flip-chip interconnection

For chip-level interconnection, nonconductive adhesive (NCA) is emerging as one of the promising substitutes for solder interconnection because of its inherent fine-pitch capability and environmental friendliness. The NCA interconnect relies on the mechanical connection between the contacts on the chip and corresponding contacts on the substrate enabled by the compressive stress created as the NCA epoxy cures. The degradation mechanism of NCA technology is, however, relatively less well understood compared to solder interconnects in terms of materials requirements for enhanced reliability performance. This study addresses the impact of material systems employed on the reliability of the packages. This involves characterization of NCA pastes in thermomechanical, hygroscopic swelling, and moisture diffusion properties. The reliability evaluation was carried out using electroless nickel/gold perimeter bumped test chips with daisy-chained connections. Analysis showed that interfacial delamination and open contact were the major failure modes in the NCA package. Pressure cooker test (PCT) performance was improved by using NCA with low-saturated moisture concentration, low coefficient of moisture expansion, and high adhesion. For better performance in the moisture sensitivity test (MST), the key properties required were high shear strength and low moisture diffusivity. Interestingly, filler content shows opposing behavior in the MST versus the PCT. Thus, optimum filler content must be found.     

Gold Stud Bumps Flip-Chip Bonded onto Copper Electrodes with Titanium and Silver Layers

The purpose of this study was to develop the thermosonic flip-chip bonding process for gold stud bumps bonded onto copper electrodes on an alumina substrate. Copper electrodes were deposited with silver as the bonding layer and with titanium as the diffusion barrier layer. Deposition of these layers on copper electrodes improves the bonding quality between the gold stud bumps and copper electrodes. With appropriate bonding parameters, 100% bondability was achieved. Bonding strength between the gold stud bumps and copper electrodes was much higher than the value converted from the standards of the Joint Electron Device Engineering Council (JEDEC). The effects of process parameters, including bonding force, ultrasonic power, and bonding time, on bonding strength were also investigated. Experimental results indicate that bonding strength increased as bonding force and ultrasonic power increased and did not deteriorate after prolonged storage at elevated temperatures. Thus, the reliability of the high-temperature storage (HTS) test for gold stud bumps flip-chip bonded onto a silver bonding layer and titanium diffusion barrier layer is not a concern. Deposition of these two layers on copper electrodes is an effective and direct method for thermosonic flip-chip bonding of gold stud bumps to a substrate, and ensures excellent bond quality. Applications such as flip-chip bonding of chips with low pin counts or light-emitting diode (LED) packaging are appropriate.     

厚膜金导体的可靠性试验

介绍了厚膜金导体可靠性试验方面的一些研究结果。对金的电化学迁移以及厚膜金导体的热试验进行了分析 ,并讨论了在工艺过程中应注意的一些问题。