Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

The use of deep-submicrometer (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of a chip. In this paper, we present a technique that reduces crosstalk noise on instruction buses. While previous research focuses primarily on address buses, little work can be applied efficiently to instruction buses. This is due to the complex transition behavior of instruction streams. Based on instruction sequence profiling, we exploit an architecture that encodes pairs of bus wires and permute them in order to optimize power and noise. A close to optimal architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 50.79% and power consumption up to 55% on instruction buses.     

A transition-encoded dynamic bus technique for high-performance interconnects

This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short-length buses, while obtaining energy savings at aggressive delay targets. On a 180-nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement using this technique.     

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3–4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead due to this technique in most of the cases.     

Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.     

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%)     

Output gating performance overhead elimination for scan test

Switching activity is much higher in test mode as compared to normal mode of operation which causes higher power dissipation, and this leads to several reliability issues. Output gating is proposed as a very effective low-power test technique, which is used to eliminate redundant switching activity in the combinational logic of circuit under test (CUT) during the shifting of test vectors in a scan chain. This method reduces the average power significantly, but it introduces performance overhead in normal mode of operation. In this work, a new output gating technique is proposed which eliminates redundant switching activity in combinational logic of CUT during shifting of test vectors without any negative impact on performance as compared to earlier proposed output gating techniques. The proposed design also improves the performance of the scan flop in functional mode with negligible area overhead incurred due to extra transistors. Experimental results show that our design has a more robust performance over wide range of capacitive load as compared to earlier designs.     

Adaptive power gating of 32-bit Kogge Stone adder

Static power consumes a significant portion of the available power budget. Consequently, leakage current reduction techniques such as power gating have become necessary. Standard global power gating approaches are an effective method to reduce idle leakage current, however, global power gating does not consider partially idle circuits and imposes significant delay and routing constraints. An adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16 nm FinFET technology node. This high granularity adaptive power gating approach employs a local controller to lower energy use and reduce circuit overhead. The controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks. Moreover, the local controller reduces routing complexity since a global power gating signal is not required. The proposed adaptive power gating technique exhibits significant energy savings, ranging from 8% to 21%. This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques. A 12% delay overhead results in a 5% area overhead. This delay overhead is reduced to 5% by increasing the area overhead to 16%, and can be further reduced by trading off additional area.     

AHB总线分析及从模块设计

AMBA总线结构广泛应用于片上系统设计中,其中AHB总线用于系统中高性能、高时钟速率模块间通信。AHB总线接口设计技术是片上系统设计的基本技术。AHB总线接口设计划分为主控模块接口设计及从模块接口设计。在详细论述AHB总线工作原理后,重点介绍了SRAM从模块AHB接口设计,包括SRAM读写控制信号的时序要求,传输操作时插入等待状态的方法,以及响应信号的产生。     

越野自主车的远距离超声测障系统

在地面自主车辆的导航与控制研究中,超声测障系统对于提高自主车的环境感知能力具有重要作用。面向野外环境自主车应用,设计并实现了一个远距离超声测障系统。该系统由超声传感器阵列、CAN总线通信模块,以及障碍检测上位机软件构成。通过时变增益电路提高了超声传感器的发射功率并减小了死区距离;基于自主车控制系统的CAN总线,设计并实现了超声测障系统的通信模块,实现了超声传感器信号的实时采集,并通过CAN总线传送到上位机。野外环境中的实验结果表明,超声测障系统具有良好的探测范围与测距精度。     

Low-power scan design using first-level supply gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.     

A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis

Research work done has shown that power consumption in digital integrated circuits can be effectively reduced by reducing the switching activity occurring on the functional modules. High-level synthesis of digital integrated circuits for low power often optimizes the switching activity during the two main synthesis processes, operation scheduling and module binding, which are usually performed one control step at a time in two separated stages. As the two processes are strongly interdependent, separate optimization of switching activity in a step-by-step manner frequently leads to sub-optimal solutions. In this paper, we propose a novel look-ahead synthesis technique with backtracking for the reduction of switching activity in low power high-level synthesis, which not only performs the scheduling and binding simultaneously in an integrated manner using a weighted bipartite technique, but also employs a branch and bound approach with look-ahead evaluation of switching activity for one or more control steps. The look-ahead technique generates multiple schedulings and bindings at the same time in one control step and uses each of them to generate more schedulings and bindings for the next one or more control steps. The best scheduling and binding pattern is then used for backtracking, therefore, effectively reducing the probability for the solutions to fall into local minimum. We tested the look-ahead algorithm with several published benchmarks and the experimental results obtained show that the switching activity can be reduced significantly, with an average of more than 50% reduction in switching activity for the tested benchmarks.     

Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses

This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-/spl mu/m TSMC CMOS technology and applied to a 4500-/spl mu/m long Metal4 bus. Circuit simulation results for different bus widths are presented.     

Low-power instruction bus encoding for embedded processors

This paper presents a low-power encoding framework for embedded processor instruction buses. The encoder is capable of adjusting its encoding not only to suit applications but furthermore to suit different aspects of particular program execution. It achieves this by exploiting application-specific knowledge regarding program hot-spots, and thus identifies efficient instruction transformations so as to minimize the bit transitions on the instruction bus lines. Not only is the switching activity on the individual bus lines considered but so is the coupling activity across adjacent bus lines, a foremost contributor to the total power dissipation in the case of nanometer technologies. Low-power codes are utilized in a reprogrammable application specific manner. The restriction to two well-selected classes of simply computable, functional transformations delivers significant storage benefits and ease of reprogrammability, in the process obtaining significant power savings. The microarchitectural support enables reprogrammability of the encoding transformations in order to track code particularities effectively. Such reprogrammability is achieved by utilizing small tables that store relevant application information. The few transformations that result in optimal power reductions for each application hot-spot are selected by utilizing short indices stored into a table, which is accessed only once at the beginning of the transformed bit sequence. Extensive experimental results show significant power reductions ranging up to 80% for switching activity on bus lines and up to 70% when bus coupling effects are also considered.     

Bus-switch coding for reducing power dissipation in off-chip buses

We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving off-chip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reordering of bus line positions, in order to minimize the toggling activity on physical bus wires. The effectiveness of the approach is demonstrated through cycle-accurate simulation of industrial benchmarks in conjunction with post-layout evaluation of speed, power and area overhead.     

DCG: deterministic clock-gating for low-power microprocessor design

With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which effectively reduces clock power. DCG is based on the key observation that for many of the pipelined stages of a modern processor, the circuit block usage in the near future is known a few cycles ahead of time. Our experiments show an average of 19.9% reduction in processor power with virtually no performance loss for an eight-issue, out-of-order superscalar by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers.     

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 μm, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1×, 2×, 3×, and 4× are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers     

Direct Power Control of Active Filters With Averaged Switching Frequency Regulation

This paper has developed a direct power control (DPC) structure to improve the performance of an active filter. A control algorithm directly uses the instantaneous power terms as control variables to replace the current and voltage variables that are commonly used in proportional-integral (PI) control systems. Compared to the other DPC schemes that have been reported so far, the proposed algorithm is oriented to harmonic current compensation, for which the switching functions are redefined, the bandwidths of the two hysteresis comparators are dynamically adjusted, and consequently, the pulsewidth modulation (PWM) switching frequencies are regulated to eliminate the unnecessary short switching pulses, and the control system can be used directly and effectively for various types of nonlinear load compensation. With the proposed control scheme, full control of the active filter, including the line current and the dc bus voltage, can be realized within an integrated power control loop. The advantages of the proposed control strategy have been verified by simulation and experimental results on a 2-kVA laboratory prototype.      

智能家居控制装置的设计与实现

针对现有智能家居控制系统存在人机交互不便、便携性与兼容性比较差等缺点,设计一种以STM32微控制器为控制核心的智能家居控制装置。该装置采用主机与执行模块分离,通过无线WiFi进行通信;执行模块利用红外线与继电器实现对家居的控制;主机采集家电的遥控器发出的红外线波形,再把原样波形的数据传输给执行模块来控制家电设备;采用PWM等效电压控制方法来调整PWM信号占空比,实现光立方的立体动态显示;使用语音识别与光立方模块进行立体动态显示和语音反馈。经实验测试表明,该装置实现了对智能家居的有效控制,具有较好的兼容性与便携性,克服了现有装置的缺点。     

A switched memory decoding circuit for bus oriented microprocessor systems

Switched memory decoding can be of considerable practical use in the development of microprocessor systems, particularly embedded microprocessor systems, in situations when prototypes for evaluation are required at an early stage. In the case of bus oriented microprocessor systems, a switched memory decoding module can be conveniently designed on a single printed circuit, which can be plugged into the bus during development and prototype evaluation, and then replaced by a permanent memory in the final unit. In this paper the design of a switched memory decoding circuit is described, which can be used in bus oriented microprocessor systems equipped with the MC6800 MPU.     

Entropy thresholding and its parallel algorithm on thereconfigurable array of processors with wider bus networks

Thresholding is the most commonly used technique in image segmentation. We first propose an efficient sequential algorithm to improve the relative entropy-based thresholding technique. This algorithm combines the concepts of the relative entropy with that of the local entropy and also includes the quadtree hierarchical structure in it. Second, we derive a constant time parallel algorithm to solve this problem on the reconfigurable array of processors with wider bus networks (RAPWBN). The system bus bandwidth determines the capacity of data communication between processors. According to the results as shown by Li and Maresca (1989) and by Maresca and Li (1989), we know that the silicon area used by the switching control mechanism is far less than that used by the processor. Instead of increasing the number of processors, we extend the number of buses to increase the power of a parallel processing system. Such a strategy of utilizing the reconfigurable array of processors with wider bus networks not only has the advantage of saving silicon area but also increases the system power enormously. So, we use the RAPWBN to solve the entropy-based thresholding problem.