基于EXIT图和自适应微粒群算法的度分布对优化方法

综合EXIT图法和自适应微粒群优化(APSO)算法的优点,该文提出了一种基于EXIT图和APSO算法的非正则LDPC码度分布对优化方法。该方法设计了衡量EXIT曲线匹配程度的全局代价函数,并运用APSO算法对度分布对进行快速迭代优化,迭代过程中不需要固定CND曲线,可以获得EXIT曲线更加匹配的优化度分布对,以及更高的噪声门限。仿真结果表明,该方法在码结构优化方面有着很好的性能,且优化速度较高斯逼近法有了较大提高。     

Rice信道下LDPC码密度进化的研究

应用低密度奇偶校验(LDPC)码译码消息的密度进化可以得到码集的噪声门限,依此评价不同译码算法的性能,并可以用来优化非正则LDPC码的次数分布对。该文首先以Rice信道下正则LDPC码为例,讨论了不同量化阶数及步长时BP,BP-based 和offset BP-based 3种译码算法的DDE(Discrete Density Evolution)分析,接着在offset BP-based译码算法的DDE分析基础上,采用差分进化方法对Rice信道下非正则LDPC码的次数分布对进行了优化,得出了相应的噪声门限。最后,给出了Rice信道下码率为1/2的优化非正则LDPC码的概率聚集函数(PMF)进化曲线。     

解码前传半双工中继信道下协作LDPC码设计

为逼近解码前传半双工中继信道容量,该文提出一种协作LDPC编码结构及度分布优化方法。与双层删除LDPC码不同,该结构将中继校验比特视为协作LDPC码的一部分,目的端利用从信源和中继接收的消息进行联合译码获得信源信息。为了分析协作LDPC码性能,拓展传统外信息转移(EXIT)图,推导了基于消息错误概率的双层EXIT图噪声门限分析方法。在此基础上,提出了协作LDPC码度分布优化方法,采用差分进化算法搜索了一组具有最大噪声门限的协作LDPC码。实验仿真证明,与双层删除LDPC码相比,协作LDPC码的性能得到了不同程度的改善。     

基于DS-CDMA系统的PDA+LDPC双迭代接收机

本文针对DS-CDMA系统来给出PDA＋LDPC双迭代接收机,该双迭代接收机由随机数据联合检测检测器（PDA）和LDPC译码器级联而成。PDA检测器可与LDPC译码器通过外迭代运算交互信息来提高系统性能。LDPC译码器由变量节点译码器（VND）和校验节点译码器（CND）组成,在每一次外迭代运算过程中,VND与CND通过一定次数的内迭代运算来交互信息。本文考虑当总的LDPC迭代译码次数一定时,选择不同的外迭代运算次数和内迭代运算次数对系统性能的影响,研究结果表明,当多址干扰量较小时,减少内迭代运算次数（增大外迭代运算次数）可获得较好的系统性能;而当多址干扰量较大时,适当增加内迭代运算次数（减小外迭代运算次数）可获得更好的系统性能。     

纠删信道中LDPC码EXIT曲线匹配设计

基于单栓码和重复码EXIT图面积特性的分析,介绍了在二元纠删信道中,采用EXIT曲线匹配设计LDPC码度分布序列的最佳性:当内外码的EXIT曲线完全匹配时,所设计的度分布序列对应的速率能够达到信道容量;而当内外码EXIT曲线之间有间隔时,所设计的度分布序列对应的速率严格小于信道容量,并且间隔面积越大,所损失的速率越大.     

LDPC码EXIT曲线图分析方法研究

EXIT曲线图是ten Brink发明的分析迭代和积译码收敛性能的有效工具。在描述了LDPC码迭代译码器结构基础上,详细地推导和研究了在AWGN信道中EXIT曲线图性能分析方法的计算方法。利用此方法确定了多种度分布LDPC码的收敛门限,并与利用高斯近似和密度进化得到的仿真结果进行比较分析,探讨EXIT曲线图的优点和进一步应用前景。     

LDPC码的优化设计

通过码结构优化设计,可以得到性能接近香农限的LDPC好码,其关键是寻找好的次数分布对。本文阐述了几种有效分析LDPC码性能的方法：密度演进分析,高斯近似分析及基于EXIT图的方法,在此基础上给出了LDPC码优化设计的过程。LDPC码结构设计的研究对提高码的性能和进一步推动LDPC码的实际应用有着重要的意义。     

基于EXIT Chart的码率兼容LDPC码的构造

提出了一种码率兼容LDPC(Rate-Compatible LDPC,以下简称RC-LDPC)码的构造方法.通过该方法构造所得到的一个高码率LDPC码的校验矩阵(H矩阵)中所包含的其它低码率LDPC码的度分布对都是通过码率兼容约束EXIT Chart优化得到.仿真结果表明这样优化得到的各个码率的LDPC码性能与采用普通的最优约束EXIT Chart优化所得到的LDPC码的性能接近.     

基于EXIT曲线图的IRA码译码方法研究

基于IRA码迭代译码器结构,研究了EXIT曲线图性能分析方法。利用此方法求出几种码率IRA码的收敛门限值,并与高斯近似和密度进化方法求得的结果进行比较分析,探讨EXIT曲线图的优点和应用技术。     

利用EXIT图分析信源码率对双LDPC码系统的影响

双LDPC( DLDPC)码系统是一种高性能的信源信道联合编码系统,但是其性能在很大程度上受到信源码率的影响。为了从理论上分析信源码率对DLDPC码系统的影响,推导了外信息转移( EX-IT)函数,并利用EXIT图分析了信源码率对DLDPC码系统的影响,理论分析结果与实际仿真结果一致。进而利用EXIT图估算出DLDPC码系统在不同信源熵情况下的信源码率门限值,该门限值可以用来指导实际系统中信源码率的选取。所提出的分析方法比传统的蒙特卡罗仿真法更加简捷、直观。     

基于EXIT图分析的BICM-ID系统SNR估计失配研究

研究了基于LDPC码的BICM-ID系统中,信道的SNR估计失配对于接收机性能的影响.提出了采用EX-IT图的分析方法,比较SNR过估计和欠估计对于解调器以及LDPC码译码器性能的影响,该方法不需要BER性能的仿真,简单直观.仿真结果表明不管是对于解调器还是LDPC码译码器,SNR过估计的影响相对较大,而欠估计则对性能的影响较小.     

Design of Irregular LDPC Codes for BIAWGN Channels with SNR Mismatch

Belief propagation (BP) algorithm for decoding lowdensity parity-check (LDPC) codes over a binary input additive white Gaussian noise (BIAWGN) channel requires the knowledge of the signal-to-noise ratio (SNR) at the receiver to achieve its ultimate performance. An erroneous estimation or the absence of a perfect knowledge of the SNR at the decoder is referred to as ?SNR mismatch?. SNR mismatch can significantly degrade the performance of LDPC codes decoded by the BP algorithm. In this paper, using extrinsic information transfer (EXIT) charts, we design irregular LDPC codes that perform better (have a lower SNR threshold) in the presence of mismatch compared to the conventionally designed irregular LDPC codes that are optimized for zero mismatch. Considering that min-sum (MS) algorithm is the limit of BP with infinite SNR over-estimation, the EXIT functions generated in this work can also be used for the efficient analysis and design of LDPC codes under the MS algorithm.     

Bandwidth-Efficient Modulation Codes Based on Nonbinary Irregular Repeat–Accumulate Codes

Using nonbinary low-density parity-check (LDPC) codes with random-coset mapping, Bennatan and Burshtein constructed bandwidth-efficient modulation codes with remarkable performance under belief propagation (BP) decoding. However, due to the random nature of LDPC codes, most of the good LDPC codes found in the literature do not have a simple encoding structure. Thus, the encoding complexity of those LDPC codes can be as high as O(N ²), where N is the codeword length. To reduce the encoding complexity, in this paper, nonbinary irregular repeat-accumulate (IRA) codes with time-varying characteristic and random-coset mapping are proposed for bandwidth-efficient modulation schemes. The time-varying characteristic and random-coset mapping result in both permutation-invariance and symmetry properties, respectively, in the densities of decoder messages. The permutation-invariance and symmetry properties of the proposed codes enable the approximations of densities of decoder messages using Gaussian distributions. Under the Gaussian approximation, extrinsic information transfer (EXIT) charts for nonbinary IRA codes are developed and several codes of different spectral efficiencies are designed based on EXIT charts. In addition, by proper selection of nonuniform signal constellations, the constructed codes are inherently capable of obtaining shaping gains, even without separate shaping codes. Simulation results indicate that the proposed codes not only have simple encoding schemes, but also have remarkable performance that is even better than that constructed using nonbinary LDPC codes.     

Design of low-density parity check codes for MIMO systems with doubly-iterative receivers

In this paper, the Multiple Input Multiple Output (MIMO) doubly-iterative receiver which consists of the Probabilistic Data Association detector (PDA) and Low-Density Parity-Check Code (LDPC) decoder is developed. The receiver performs two iterative decoding loops. In the outer loop, the soft information is exchanged between the PDA detector and the LDPC decoder. In the inner loop, it is exchanged between variable node and check node decoders inside the LDPC decoder. On the light of the Extrinsic Information Transfer (EXIT) chart technique, an LDPC code degree profile optimization algorithm is developed for the doubly-iterative receiver. Simulation results show the doubly-receiver with optimized irregular LDPC code can have a better performance than the one with the regular one.     

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.     

Overlapped message passing for quasi-cyclic low-density parity check codes

In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.     

RS码与LDPC码的联合迭代译码

针对RS码与LDPC码的串行级联结构,提出了一种基于自适应置信传播(ABP)的联合迭代译码方法.译码时,LDPC码置信传播译码器输出的软信息作为RS码ABP译码器的输入;经过一定迭代译码后,RS码译码器输出的软信息又作为LDPC译码器的输入.软输入软输出的RS译码器与LDPC译码器之间经过多次信息传递,译码性能有很大提高.码长中等的LDPC码采用这种级联方案,可以有效克服短环的影响,消除错误平层.仿真结果显示:AWGN信道下这种基于ABP的RS码与LDPC码的联合迭代译码方案可以获得约0.8 dB的增益.     

基于FFT-BP算法的多元域LDPC码译码器设计与FPGA实现

GF(q)域上的LDPC码是二进制LDPC码的扩展,它具有比二进制LDPC码更好的纠错性能。FFT-BP算法是高效的LDPC码译码算法,本文在GF(4)域上探讨该算法的设计与实现。本文的创新之处在于,根据FFT-BP算法的特点设计了一种利用Tanner图进行信息索引的方式,简化了地址查询模块的设计。实验表明,在归一化信噪比为2.6dB时,译码器的误码率可达到10-6。     

多元LDPC译码器设计

在多元低密度奇偶校验码(NB-LDPC)的扩展最小和译码算法（EMS）中,由于消息向量的递归计算和校验/变量节点信息之间的迭代交换,导致译码器存在较大延迟。针对此问题本文提出了一种新型译码器结构,它优化了校验节点更新单步运算单元,根据前向后向算法规则,以3路单步运算单元完成校验节点更新,硬件资源消耗略有增加,但所需时钟周期约降为一般结构的1/3;并采用全并行运算的变量节点信息更新单元,无需利用前向后向算法将更新过程分解为多个单步运算,消除了变量节点更新的递归计算,且具有低复杂度低延时等优点,并在现场可编程门阵列(FPGA)Xilinx Virtex-4 (XC4VLX200)平台上对一个GF(16)域上(480,360)的准循环多元LDPC码进行了综合仿真。仿真结果证明,设计的译码器在较小资源消耗条件下能成倍提高吞吐量。