Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Low-Voltage and High-Speed Operations of 30-nm-Gate Pseudomorphic $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}/hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$ HEMTs Under Cryogenic Conditions

In this letter, we fabricated 30-nm-gate pseudomorphic In_0.52 Al_0.48As/In_0.7Ga_0.3As HEMTs with multilayer cap structures to reduce source and drain parasitic resistances; we measured their dc and radio-frequency characteristics at 300, 77, and 16 K under various bias conditions. The maximum cutoff frequency fT was 498 GHz at 300 K and 577 GHz at 77 K. The maximum fT exceeded 600 GHz at 16 K. Even at a drain-source voltage V _ds of 0.4 V, we obtained an fT of 500 GHz at 16 K. This indicates that cryogenic HEMTs are favorable for low-voltage and high-speed operations. Furthermore, the present 30-nm-gate HEMTs at 300 K show almost the same fT values at the same dc-power dissipation as compared to 85-nm-gate InSb-channel HEMTs. The improvement of the maximum-oscillation-frequency f _max values was also observed at 77 and 16 K.     

Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $hbox{Dy}_{2}hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy₂O₃ cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy₂O₃ cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy₂O₃ cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS.     

A Theoretical Comparison of the Breakdown Behavior of $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ and InP Near-Infrared Single-Photon Avalanche Photodiodes

We study the breakdown characteristics and timing statistics of InP and $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ single-photon avalanche photodiodes (SPADs) with avalanche widths ranging from 0.2 to 1.0 $mu{hbox {m}}$ at room temperature using a random ionization path-length model. Our results show that, for a given avalanche width, the breakdown probability of $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs increases faster with overbias than InP SPADs. When we compared their timing statistics, we observed that, for a given breakdown probability, InP requires a shorter time to reach breakdown and exhibits a smaller timing jitter than $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ . However, due to the lower dark count probability and faster rise in breakdown probability with overbias, $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs with $hbox{avalanche} hbox{widths}leq 0.5 mu{hbox {m}}$ are more suitable for single-photon detection at telecommunication wavelengths than InP SPADs. Moreover, we predict that, in InP SPADs with $hbox{avalanche} hbox{widths}leq 0.3 mu{hbox {m}}$ and $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs with $hbox{avalanche} hbox{widths}leq 0.2 mu{hbox {m}}$, the dark count probability is higher than the photon count probability for all applied biases.      

35-nm Zigzag T-Gate $hbox{In}_{0.52}hbox{Al}_{0.48} hbox{As/In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Metamorphic GaAs HEMTs With an Ultrahigh $f_{max}$ of 520 GHz

Metamorphic GaAs high electron mobility transistors (mHEMTs) with the highest-f _max reported to date are presented here. The 35-nm zigzag T-gate In_0.52Al_0.48As/In_0.53Ga_0.47As metamorphic GaAs HEMTs show f _maxof 520 GHz, f _T of 440 GHz, and maximum transconductance (g _m) of 1100 mS/mm at a drain current of 333 mA/mm. The combinations of f _max and f _T are the highest data yet reported for mHEMTs. These devices are promising candidates for aggressively scaled sub-35-nm T-gate mHEMTs.     

A Two-Step-Recess Process Based on Atomic-Layer Etching for High-Performance $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}hbox{/}hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ p-HEMTs

We investigated 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Aring/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In_0.52Al_0.48As barrier layer, and an rms surface-roughness value of 1.37 Aring for the exposed In_0.52Al_0.48As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As p-HEMTs produced improved device parameters, including transconductance (G_M), cutoff frequencies (f_T)> and electron saturation velocity (vsat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As p-HEMTs fabricated by using the ALET technology exhibited G_M,_Max = 1-17 S/mm, f_T = 398 GHz, and v_sat = 2.5 X 10⁷ cm/s.     

Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $hbox{La}_{2}hbox{O}_{3}/hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High- $kappa$ Dielectrics and Si Channel

In this letter, we report that by employing the La₂O₃/SiO_x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta₂C metal-gated n-MOSFETs V_T can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J_G = 10 mA/cm² at 1.1 V), good drive performance (I_on = 900 muA/mum at I_soff = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.     

Numerical Study of Flicker Noise in p-Type $ hbox{Si}_{0.7}hbox{Ge}_{0.3}/hbox{Si}$ Heterostructure MOSFETs

Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si_0.7Ge_0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices.     

Lateral and Vertical Scaling of $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications

In this paper, we have experimentally investigated the impact of lateral and vertical scaling of In_0.7Ga_0.3As high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the In_0.52Al_0.48As insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature V_T = -0.02 V, DIBL = 93 mV/V, S = 88 mV/V, and I_ON/I_OFF = 1.6 times10⁴, at V _DD = 0.5 V. We also estimate a gate delay of CV/I = 1.6 ps at V_DD = 0.5 V. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit 1.2times more current drive (I_ON) than the state-of-the-art 65-nm low-power CMOS technology at V _DD = 0.5 V.     

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

A Monte Carlo Study of $hbox{Hg}_{0.7}hbox{Cd}_{0.3}hbox{Te}$ e-APD

A simple Monte Carlo model is developed for understanding the multiplication process in HgCdTe infrared avalanche photodiodes and the impact of physical and technological parameters. A good agreement is achieved between simulations and experimental measurements of gain and excess noise factor. In both cases, an exponential gain and extremely low noise—$F sim hbox{1}$ for multiplication gains up to 1000—were observed on 5.1-$muhbox{m}$ cutoff devices at 77 K, indicative of a single carrier impact ionization. A comparison study is presented to explain the effect of different combinations of scattering processes on the avalanche phenomenon in HgCdTe.      

Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

Low Turn-On Voltage and High-Current $hbox{InP}/ hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Double Heterojunction Bipolar Transistors

We report on the dc and microwave characteristics of an $ hbox{InP/In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ double heterojunction bipolar transistor grown by solid-source molecular beam epitaxy. The pseudomorphic $hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}$ base reduces the conduction band offset $Delta E_{C}$ at the emitter/base junction and the base band gap, which leads to a very low $V_{rm BE}$ turn-on voltage of 0.35 V at 1 $hbox{A/cm}^{2}$ . A current gain of 125 and a peak $f_{T}$ of 238 GHz have been obtained on the devices with an emitter size of $hbox{1}times hbox{10} muhbox{m}^{2}$, suggesting that a high collector average velocity and a high current capability are achieved due to the type-II lineup at the InGaAsSb/InGaAs base/collector junction.      

0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFET

We report the experimental demonstration of deep-submicrometer inversion-mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFETs with ALD high- $k$ $hbox{Al}_{2}hbox{O}_{3}$ as gate dielectric. In this letter, n-channel MOSFETs with 100–200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200–130-nm-long gates exhibit drain currents of 232–440 $muhbox{A}/muhbox{m}$ and transconductances of 538–705 $muhbox{S}/muhbox{m}$. The 100-nm device has a drain current of 801 $muhbox{A}/muhbox{m}$ and a transconductance of 940 $muhbox{S}/muhbox{m}$. However, the device cannot be pinched off due to severe short-channel effect. Important scaling metrics, such as on/off current ratio, subthreshold swing, and drain-induced barrier lowering, are presented, and their relations to the short-channel effect are discussed.      

Negative Differential Resistance in Buried-Channel $hbox{Ge}_{x} hbox{C}_{1 - x}$ pMOSFETs

We study the device characteristics of Si-capped $hbox{Ge}_{x}hbox{C}_{1 - x}$ pMOSFETs from room temperature down to 77 K. The output characteristics of these devices reveal a negative differential resistance (NDR) at temperatures below 150 K. Our measurements indicate a higher effective carrier mobility in the buried-channel $hbox{Ge}_{x}hbox{C}_{1 - x}$ with respect to the Si-reference sample, which suggests that the observed NDR is due to real-space transfer of hot holes from the higher mobility $hbox{Ge}_{x}hbox{C}_{1 - x}$ channel layer into the lower mobility Si cap layer.      

Actively $Q$ -switched and Mode-Locked Diode-Pumped ${hbox {Nd:GdVO}}_{4}{hbox {--KTP}}$ Laser

By using a comparative simple configuration and a short cavity length, a diode-pumped actively Q -switched and mode-locked intracavity frequency doubled Nd:GdVO₄-KTP green laser with the modulation depth 100% was realized, from which the great average output power, the high efficiency were obtained and the mode-locked pulse inside the Q -switched pulse has a repetition rate of 476 MHz. Using the hyperbolic secant function methods and by considering the Gaussian distribution of the intracavity photon density, the influences of continuous pump rate, the upper state lifetime of the active medium and the turnoff time of the acousto-optic Q -switch, we proposed a developed rate equation model for actively Q -switched and mode-locked green lasers. With this developed model, the theoretical calculations are in good agreement with the experimental results and the width of the mode-locked green pulse is estimated to be about 185 ps.     

Pentacene-Based Low-Voltage Strain Sensors With PVP/$ hbox{Ta}_{2}hbox{O}_{5}$ Hybrid Gate Dielectrics

Field-controllable pentacene-semiconductor-based strain sensors were fabricated with hybrid gate dielectrics using polyvinyl phenol (PVP) and high-$k$ inorganic tantalum pentoxide $(hbox{Ta}_{2}hbox{O}_{5})$ onto polyethylene naphthalate films. The $hbox{Ta}_{2}hbox{O}_{5}$ gate-dielectric layer combined with a thin PVP layer to form very smooth and hydrophobic surfaces turns out to improve the molecular structures of pentacene films significantly. The PVP– $hbox{Ta}_{2}hbox{O}_{5}$ hybrid-gate-dielectric films exhibit a high dielectric constant of 19.27 and a leakage-current density of as low as 100 $hbox{nA/cm}^{2}$ . The sensors employing a thin-film-transistor-like Wheatstone bridge configuration able to operate at reduced voltage ($sim$4 V) show good device characteristics with a field-effect mobility of 1.89 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and a threshold voltage of $-$0.5 V. The strain sensor characterized with bending at 45$^{circ}$ with respect to the bridge bias direction with different bending radii of 50-, 40-, 30-, 20-, and 8-mm displays output signals improved in linearity in a low range of operating voltages.      

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.