High-speed operation of a low-power 4-bit serial-to-parallel converter

This paper presents a high-speed low-power 4-bit superconducting serial-to-parallel converter (SPC) that has been demonstrated experimentally to operate at data rates up to 1 Giga-bits (Gb/s). The primary design goals for this device are high-speed operation, low-power dissipation, and high circuit yield for use as a core element in an address decoder or a demultiplexer. First, the circuit design and optimization are discussed. Simulated performance of the circuit shows proper operation at 20 Gb/s, with a discussion of its potential for use at even higher rates. The power dissipation is computed to be 28 /spl mu/W in continuous operation and the predicted within-wafer yield is 95%. Measured results are then given for data rates of 100 Mb/s and 1 Gb/s.     

Design, fabrication and operation of a hot electron resonant tunneling transistor

Transistors employing resonant tunneling injection of hot electrons into a thin quantum well base region have been fabricated. The base region in these transistors is formed by a narrow bandgap material like InGaAs so that the first level is a confined one lying below the Fermi level in the contact regions. This results in charge transfer into the bound state in the quantum well thus allowing independent control of the base electrostatic potential. Theoretical calculations showing the importance of various device parameters in the design of a resonant tunneling transistor are presented and preliminary results showing the capability of transistor action in such devices are presented.     

High-speed and low-power GaAs DCFL divider

High-speed and low-power divide-by-252 or -256 circuit have been fabricated by using high-transconductance GaAs enhancement-mode MESFETs. This variable-modulus divider is able to operate up to a clock frequency of 3.7 GHz. The total power dissipation at the maximum frequency is 180 mW, and it is as low as 42 mW and 30 mW at 3 GHz and 2.5 GHz, respectively.     

High-speed and low-power CMOS priority encoders

The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively. Second, this look-ahead structure is realized efficiently by the NP Domino CMOS logic, and all the dynamic gates have a parallel-connected circuit structure. For high speed and low power at the same time, the series-connected circuit structure is adopted in the less critical paths to reduce the switching activity, but such a design needs to cascade two n-type dynamic gates directly resulting in the race problem. A special circuit technique is utilized to rescue this problem. Several 32-bit priority encoders are designed to evaluate the feasibility of the proposed techniques. The best new design realizes a three-level look-ahead structure, and it achieves 65% speed improvement, 20% layout area reduction, and 30% power reduction simultaneously as compared to the conventional design with a simple look-ahead structure     

InP基共振遂穿二极管器件（RTD）研究

我们在实验中对InGaAs/AlAs/InP共振遂穿二极管（RTD）材料结构进行了优化设计,并用MBE设备在(100)半绝缘InP单晶片上生长了RTD外延材料。我们采用电子束光刻工艺和空气桥互连技术,制作了InP基RTD器件。并在室温下测试了器件的电学特性：峰值电流密度24.6kA/cm2,峰谷电流比(PVCR)为8.6。     

Two-band combined model of a resonant tunneling diode

A two-band combined model of a resonant tunneling diode, based on the semiclassical and quantum mechanical (the wave function formalism) approaches is proposed. The main specific feature of this model is the possibility of taking into account the interaction between different classical or quantum mechanical device regions with simultaneous consideration of the Γ-X intervalley scattering. It is shown that this model gives satisfactory agreement with the experimental data on the current-voltage characteristics and allows explanation of the plateau region in these characteristics within the stationary model.     

High-speed and low-power interconnect technology forsub-quarter-micron ASIC's

The optimum interconnect structure for high-speed and low-power sub-quarter-micron Application Specified Integrated Circuits (ASIC's) is investigated. High-speed and low-power scaling rules for the interconnect structures are extracted statistically from the wiring data in actual ASIC's. Adopting the scaling rule for a 0.25-μm ASIC enables us to reduce the gate delay by 23% and the gate power by 31% compared to conventional (horizontal only) scaling rule. A low-dielectric-constant interlayer insulator further reduces both the gate delay and power by reducing wiring capacitance. A 0.25-μm interconnect structure was fabricated by adopting the “high-speed and low-power interconnect scaling rule” and using organic spin-on-glass (SOG) as a low-dielectric-constant interlayer insulator. According to equivalent-circuit calculation using the measured interconnect parameters, the gate delay was reduced by 39% and the gate power was reduced by 47% compared to a conventional interconnect structure     

High-speed and low-power repeater for VLSI interconnects

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.     

High-speed low-power silicon MESFET parallel multipliers

The design of fast low-power silicon LSI MESFET parallel multipliers is studied. The architecture of the multipliers and the designs of the functional blocks are discussed. The overall performance of the multipliers is estimated from the simulated performances of the functional blocks and from system simulations with a logic simulator. The actual performance of 8/spl times/8 and 10/spl times/10 bit TTL-compatible multipliers, fabricated with a 2.5 /spl mu/m silicon MESFET technology (1.5-2 /spl mu/m effective dimensions) is compared to the simulations.     

High-speed low-power circuits fabricated using a submicron NMOS technology

We present results on very high-speed low-power devices and circuits fabricated using a NMOS technology scaled to submicron dimensions. These results illustrate the electrical behavior of single minimum-size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3-GHz divide-by-two counter and a 90- MHz 16 × 16 multiplier.     

High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

Generation in a microstrip-resonator-stabilized double-barrier resonant tunneling structure

Generation in a microstrip-resonator-stabilized double-barrier resonant tunneling structure based on GaAs/AlAs heterostructures has been investigated for the first time. The structures fabricated contain near-contact layers (spacers) that prevent impurities from penetrating into the active part of the structure and improve the temporal characteristics of the system. AuNiGe alloy microstrip contacts, which connect the structure with an external rf circuit, were prepared in a planar implementation, making it possible to minimize the RC delay time in the negative differential conductance region by decreasing the series resistance and capacitance of the structure. In structures with spacer layers, the negative differential conductance exhibits a complex behavior due to the influence of the space charge. Fiz. Tekh. Poluprovodn. 32, 124–127 (January 1998)     

High-speed low-power direct-coupled complementary push-pull ECLcircuit

This paper presents a high-speed low-power direct-coupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pull-down scheme with no extra biasing circuit for the push- and pull-transistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-μm double-poly self-aligned complementary bipolar process, the circuit offers 2.0X (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit     

A low-power microprocessor based on resonant energy

We describe AC-1, a CMOS microprocessor that derives most of its operating power from the clock signals rather than from dc supplies. Clock-powered circuit elements are selectively used to drive high-fan-out nodes. An inductor-based, all-resonant clock-power generator allows us to recover 85% of the clock-drive energy. The measured top frequency for the microprocessor was 58.8 MHz at 26.2 mW. The resulting overall decrease in dissipation ranges from four to five times at clock frequencies from 35 to 54 MHz. We also compare the performance of the processor to a reimplementation in static logic     

Double-barrier resonant tunneling transport model

A semiquantum transport model for electron transport in the resonant tunneling diode (RTD) is presented. The total electrons tunneling through the RTD are partitioned into two parts. The first is the coherent tunneling electrons, which do not experience any scattering except by the barriers during tunneling. These electrons are described by the damped resonant tunneling model. The second is the incoherent tunneling electrons, which are the electrons scattered in the quantum well by the phonons, impurities, etc. The hot electron distribution, which is characterized by the effective Fermi energy μ_e and electron temperature T_e, is proposed to model the nonequilibrium distribution of the incoherent electrons in the well. The parameters μ_e and T_e can be uniquely determined by applying the energy conservation law and the particle conservation law to the incoherent electrons in the well. The incoherent electrons play a major role in the operation of the RTD. The capacitance of the RTD is investigated, based on the model and Poisson's equation. Extensive numerical results are presented     

共振隧穿二极管的设计和研制

用分子束外延在半绝缘砷化镓上生长两垒一阱结构,制成RTD单管。经过材料生长设计、工艺设计和版图设计几方面的改进,测得最高振荡频率已达54GHz。     

High-speed, low-power BiCMOS comparator using a pMOS variable load

A novel BiCMOS latched comparator for high-speed, low-power applications is proposed. The resistive load of conventional current-steering comparators is replaced by a variable load made by a pMOS transistor that, during the comparison cycle, is successively biased in three different operating regions. This solution provides a lower power consumption than conventional architectures, without sacrificing sampling speed. Post-layout simulation results and measurements performed on the prototypes are presented     

Imperfections and resonant tunneling in quantum-well heterostructures

We discuss effects of structural imperfections on the I-V characteristics and local density-of-states of semiconductor double-barrier heterostructures. Using a linear-chain model for GaAs/AlGaAs structures, we simulate fluctuations in layer thicknesses, defects at the heterointerfaces, and disorder.     

Electric field switching in a resonant tunneling diodeelectroabsorption modulator

The basic mechanism underlying electric field switching produced by a resonant tunneling diode (RTD) is analyzed and the theory compared with experimental results; agreement to within 12% is achieved. The electroabsorption modulator (EAM) device potential of this effect is explored in an optical waveguide configuration. It is shown that a RTD-EAM can provide significant absorption coefficient change, via the Franz-Keldysh effect, at appropriate optical communication wavelengths around 1550 nm and can achieve up to 28-dB optical modulation in a 200-μm active length device. The advantage of the RTD-EAM over the conventional reverse-biased p-n junction EAM, is that the RTD-EAM has, in essence, an integrated electronic amplifier and, therefore, requires considerably less switching power