A 200-MHz complex number multiplier using redundant binaryarithmetic

Modern digital communication systems rely heavily on baseband signal processing for in-phase and quadrature (I-Q) channels, and complex number processing in low-voltage CMOS has become a necessity for channel equalization, timing recovery, modulation, and demodulation. In this work, redundant binary (RB) arithmetic is applied to complex number multiplication for the first time so that an N-bit parallel complex number multiplier can be reduced to two RE multiplications (i.e., an addition of N RB partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RB partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5 K transistors is integrated on 1.05×1.33 mm² using 0.8 μm CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at 200 MHz     

A 600-MHz 54×54-bit multiplier with rectangular-styledWallace tree

This paper presents an efficient layout method for a high-speed multiplier. The Wallace-tree method is generally used for high-speed multipliers. In the conventional Wallace tree, however, every partial product is added in a single direction from top to bottom. Therefore, the number of adders increases as the adding stage moves forward. As a result, it generates a dead area when the multiplier is laid out in a rectangle. To solve this problem, we propose a rectangular Wallace-tree construction method. In our method, the partial products are divided into two groups and added in the opposite direction. The partial products in the first group are added downward, and the partial products in the second group are added upward. Using this method, we eliminate the dead area. Also, we optimized the carry propagation between the two groups to realize high speed and a simple layout, We applied it to a 54×54-bit multiplier. The 980 μm×1000 μm area size and the 600 MHz clock speed have been achieved using 0.18 μm CMOS technology     

A 4.4 ns CMOS 54×54-b multiplier using pass-transistormultiplexer

A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply     

A carry-free 54b×54b multiplier using equivalent bitconversion algorithm

An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in the redundant binary (RB) to normal binary (NB) conversion step for RB multiplication. The multiplication process helps with the carry-free conversion step by eliminating certain combinations of RB product. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized carry-free converters, and the entire multiplication process can be made free of carry propagation from input to output. The method employed in this work reduces 40% of the total power and 30% of the total multiplication time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35-μm CMOS demonstrates that the 54 b×54 b multiplier consumes only 53.4 mW at 3.3 V for 74-MHz operation     

A 4.1-ns compact 54×54-b multiplier utilizing sign-selectBooth encoders

A 54×54-b multiplier with only 60 K transistors has been fabricated by 0.25-μm CMOS technology. To reduce the total transistor count, we have developed two new approaches: sign-select Booth encoding and 48-transistor 4-2 compressor circuits both implemented with pass transistor logic. The sign-select Booth algorithm simplifies the Booth selector circuit and enables us to reduce the transistor count by 45% as compared with that of the conventional one. The new compressor reduces the count by 20% without speed degradation. By using these new circuits, the total transistor count of the multiplier is reduced by 24%. The active size of the 54×54-b multiplier is 1.04×1.27 mm and the multiplication time is 4.1 ns at a 2.5-V power supply     

A 32×32-bit multiplier using multiple-valued MOS current-modecircuits

A 32×32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2-μm CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32×32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2×5.2 mm², which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported     

A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells

3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 m bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.     

Implementation of a self-resetting CMOS 64-bit parallel adder withenhanced testability

This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22°C with V_dd=2.5 V) and 300 mW. The adder core size is 1.6×0.275 mm². The process technology used was the 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs     

A 10 ns 54×54 b parallel structured full array multiplierwith 0.5 μm CMOS technology

A 54 b×54 b multiplier fabricated in a double-metal 0.5 μm CMOS technology is described. The 54 b×54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz     

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valuedMOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54×51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-μm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit     

Design of synchronous and asynchronous variable-latency pipelinedmultipliers

This paper presents a novel variable-latency multiplier architecture, suitable for implementation as a self-timed multiplier core or as a fully synchronous multicycle multiplier core. The architecture combines a second-order Booth algorithm with a split carry save array pipelined organization, incorporating multiple row skipping and completion-predicting carry-select dual adder. The paper reports the architecture and logic design, CMOS circuit design and performance evaluation. In 0.35 μm CMOS, the expected sustainable cycle time for a 32-bit synchronous implementation is 2.25 ns. Instruction level simulations estimate 54% single-cycle and 46% two-cycle operations in SPEC95 execution. Using the same CMOS process, the 32-bit asynchronous implementation is expected to reach an average 1.76 ns throughput and 3.48 ns latency in SPEC95 execution     

High-speed complex-number multiplications based on redundant binary representation of partial products

The complex-number multiplier is one of the key arithmetic components for the baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. This paper presents two algorithms suitable for a high-speed complex-number multiplier, which are based on redundant binary (RB) representation of partial products. The basic idea behind our approach is to convert a pair of binary partial products into a RB form so that the post-addition/subtraction which is inevitable in the conventional methods based on binary multiplication, is eliminated. With the proposed algorithms, the complex-number multiplication is reduced to two RB multiplications, one for the real part and the other for the imaginary part. The RB multiplication is defined by an addition of RB partial products, and is performed in parallel without carry propagation from the least-significant digit to the most-significant digit. This work results not only in simplified arithmetic operations, but also in highly parallel and simple architecture when compared with conventional methods using binary multiplications. To demonstrate the algorithms, two test chips have been implemented using a 0.8µm CMOS technology.     

BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture

In this paper, a low-power structure called bypass zero, feed A directly (BZ-FAD) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications to the multiplier which multiplies A by B include the removal of the shifting the B register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of a binary counter and removal of the partial product shift. The architecture makes use of a low-power ring counter proposed in this work. Simulation results for 32-bit radix-2 multipliers show that the BZ-FAD architecture lowers the total switching activity up to 76% and power consumption up to 30% when compared to the conventional architecture. The proposed multiplier can be used for low-power applications where the speed is not a primary design parameter.     

A BiCMOS dynamic multiplier using Wallace tree reductionarchitecture and 1.5-V full-swing BiCMOS dynamic logic circuit

The authors present a BiCMOS dynamic multiplier, which is free from race and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one     

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.     

基于忆阻器的乘法器电路设计

忆阻器作为一种非易失性的新型电路元件,在数字逻辑电路中具有良好的应用前景。目前,基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究,其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块,设计了一个2位二进制乘法器电路,另一种是结合新型的比例逻辑,即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较,并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器),相比于过去的忆阻乘法器,减少了大量晶体管的使用。     

Design and implementation of a 5×5 trits multiplier in aquasi-adiabatic ternary CMOS logic

Adiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is presented, and to validate its performance, a 5×5 ternary digit multiplier is designed and implemented in a 0.7-μm CMOS technology. Results show a satisfactory power saving with respect to conventional and other quasi-adiabatic binary multipliers, and a decrease of the area needed with respect to a fully adiabatic binary one     

A 286 MHz 64-b floating point multiplier with enhanced CG operation

This paper presents a high speed 64-b floating point (FP) multiplier that has a useful function for computer graphics (CG). The critical path delay is minimized by using high speed logic gates and limiting the stage number of series transmission gates (TGs). The high speed redundant binary architecture is applied to the multiplication of significands. This FP multiplier has a special function of “CG multiplication” that directly multiplies a pixel data by an FP data. This multiplier was fabricated by 0.5-μm CMOS technology with triple-level metal of interconnection. The active area size is 4.2×5.1 mm². The operating cycle time is 3.5 ns at the supply voltage of 3.3 V, which corresponds to the frequency of 286 MHz. Implementation of CG multiplication increases the transistor count only 4%. Also, CG multiplication has no effect on the delay in the critical path     

Circuit techniques for CMOS low-power high-performance multipliers

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS     

Minimization of switching activities of partial products for designing low-power multipliers

This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the radix-4 Booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate Booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. To further reduce power consumption, the two multipliers based on row-based and hybrid-based adder trees are realized with operations on effective dynamic ranges of input data. Functional blocks of these two multipliers can preserve their previous input states for noneffective dynamic data ranges and thus, reduce the number of their switching operations. To illustrate the proposed multipliers exhibiting low-power dissipation, the theoretical analyzes of switching activities of partial products are derived. The proposed 16 /spl times/ 16-bit multiplier with the column-based adder tree conserves more than 31.2%, 19.1%, and 33.0% of power consumed by the conventional multiplier, in applications of the ADPCM audio, G.723.1 speech, and wavelet-based image coders, respectively. Furthermore, the proposed multipliers with row-based, hybrid-based adder trees reduce power consumption by over 35.3%, 25.3% and 39.6%, and 33.4%, 24.9% and 36.9%, respectively. When considering product factors of hardware areas, critical delays and power consumption, the proposed multipliers can outperform the conventional multipliers. Consequently, the multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost or little slowing of speed.