A 0.18-$muhbox m$CMOS Selective Receiver Front-End for UWB Applications

This paper addresses the problem of 5–6-GHz WLAN interferer rejection in a direct-conversion receiver front-end for multi-band orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) applications. The IC, realized in a 0.18-$muhbox m$CMOS technology, comprises a single-ended voltage–voltage feedback low-noise amplifier (LNA) and a quadrature mixer. The LNA employs a double-peak single-notch network in the output load, amplifying UWB groups #1 and #3, while rejecting WLAN interferes in the 5–6-GHz frequency range. The mixer, based on a merged quadrature topology, also realizes a second-order low-pass filtering. Fabricated dies have been bonded on PCB for characterization. The front-end, drawing 10 mA from 1.8 V, achieves a 1-dB gain desensitization with a$-$6.5-dBm interferer power at 5.5 GHz. Other measured performances are 5.2-dB and 7.7-dB minimum and maximum noise figure (NF),$-$3.5-dBm minimum IIP3 and$+$34.5-dBm minimum in-band IIP2 and$+$21-dBm out-of-band IIP2.     

A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology

An adaptive equalizer incorporates spectrum-balancing technique to achieve high speed and low power dissipation. Obviating the need for slicers, this circuit compares the low and high frequency components of the data spectrum and adjusts the boosting accordingly. Fabricated in 0.13-$muhbox m$CMOS technology, this circuit achieves a data rate of 20 Gb/s while consuming 60mW from a 1.5-V supply.     

A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits are devised based on current mirrors, and thus, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed circuits is verified by implementing an analog MS decoder for a (32,8) LDPC code in a 0.18-mum CMOS technology. This decoder is the first reported analog MS decoder. For low signal to noise ratios where the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional floating-point discrete-time synchronous MS decoder. When data throughput is 6 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10^-3 is about 0.3 dB and power consumption is about 5 mW. This is the first time that an analog decoder has been successfully tested for an LDPC code, though a short one     

A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS

This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-$muhbox m$process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally spaced FIR equalizer is demonstrated using a low-power and area-efficient pulse extraction method as on-chip error detector. Measurement results show that the proposed adaptive equalizer achieves over 75% horizontal eye opening when the channel loss at the half-data-rate frequency varies from 4 dB to 21 dB at 2.5-Gb/s data rate. At 3.5-Gb/s data rate, the equalizer achieves 68% horizontal eye opening when the channel loss is about 9.3 dB at the half-data-rate frequency. The adaptive equalizer including the FIR filter and the error detector occupies 0.095$hbox mm^2$die area and dissipates 95 mW at 2.5-Gb/s data rate from 2.5-V voltage supply.     

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS

A clock and data recovery (CDR) architecture featuring a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding fixed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt-peaking and capacitance coupling. The monolithic CDR implemented in 0.13-$muhbox m$CMOS shows 1.7 times wider phase linear response region of 0.56UI than that of a conventional CDR. It operates at 12.5-Gb/s with PRBS$2 ^31 -1$input data. Measurements show large jitter tolerance of over 0.5 UIpp for 4-8 MHz jitter frequency as well as jitter transfer characteristics independent on input-jitter amplitudes of 0.1, 0.3, and 0.5 UIpp.     

Cost-Effective Integrated RF Power Transistor in 0.18-$muhboxm$CMOS Technology

A novel MOS power transistor with high breakdown voltage is proposed and manufactured in a standard 0.18-$muhboxm$CMOS process without any additional masks or extra process steps. A “U”-type$hboxn^-$drift region formed with shallow trench isolation (STI) layer and n-well is adopted to improve the breakdown voltage. A MOS transistor with 11.6-V breakdown voltage, 18-GHz cutoff frequency, and 30-GHz maximum oscillation frequency has been demonstrated. In addition, it has 11.5-dB power gain, 19.3-dBm output power at 2.45 GHz with power-added efficiency (PAE) of 55%, and 8.3-dB power gain 18.7-dBm output power at 5.8 GHz with PAE of 38%. The presented RF power transistor is cost effective and can be conveniently applied in the power amplifier integration for RF SoC.     

A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology

This paper describes a fully differential 1-tap decision feedback equalizer in 0.18-$muhbox m$SiGe BiCMOS technology. The circuit is capable of equalizing NRZ data up to 40 Gb/s. A look-ahead architecture is employed with modifications to reduce complexity in the high-speed clock distribution. An analog differential voltage controls the tap weights. The design is fabricated in 0.18-$muhbox m$SiGe BiCMOS technology with a 160-GHz$f_T$. It occupies an area of 1.5 mm$,times ,$1 mm and operates from a 3.3-V supply with 230-mA current. It is the first feedback equalizer at 40 Gb/s.     

Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology

A 40-GSamples/s track and hold amplifier (THA) is designed and fabricated in 0.18-$muhbox m$SiGe BiCMOS and operates from a 3.6-V supply. The total power consumption is 540 mW with a chip area of 1.1$hbox mm^2$. Time domain measurements demonstrate 40-GHz sampling and$ S$-parameter measurements show a 3-dB bandwidth of 43 GHz in track mode. For 19-GHz input signals, a total harmonic distortion of$-hbox 27~dB$at the 1dB compression point has been measured and a spurious-free dynamic range of 35 dB has been achieved.     

对智能卡进行微分功耗分析攻击的方法研究

详细阐述了对通用密码系统实施微分功耗分析攻击(DPA)的理论基础和对DES算法攻击的特定理论，并提出了对DPA的改进算法。在分析功耗信号的噪声特点以后，提出了一个信噪比(SNR)的建模方法和相应理论的证明。最后，给出了算法的一个实验结果。     

DES芯片抵御高阶差分功耗分析攻击方法研究

分析独特的屏蔽方法及改进方法的不足,提出了逻辑层和算法层相结合抵御高阶差分功耗分析攻击的新方法,并给出芯片半定制设计流程.芯片关键部分电路采用自定义功耗恒定逻辑单元实现,非关键部分电路采用CMOS逻辑以减少功耗和面积.整体电路采用独特的屏蔽方法自定义轮实现.结果表明芯片能够抵御高阶差分功耗分析攻击,运算速度与现有方法相当,而所需资源比现有方法少.     

DES芯片抵御高阶差分功耗分析攻击方法研究

分析独特的屏蔽方法及改进方法的不足,提出了逻辑层和算法层相结合抵御高阶差分功耗分析攻击的新方法,并给出芯片半定制设计流程.芯片关键部分电路采用自定义功耗恒定逻辑单元实现,非关键部分电路采用CMOS逻辑以减少功耗和面积.整体电路采用独特的屏蔽方法自定义轮实现.结果表明芯片能够抵御高阶差分功耗分析攻击,运算速度与现有方法相当,而所需资源比现有方法少.     

分组密码DPA汉明重量区分函数选择方法

为了解决分组密码差分能量分析攻击(DPA)汉明重量区分函数选择问题,提出了一种基于相对非线性度的选择方法.该方法利用分组密码算法S盒输出相对非线性度与DPA之间的关系,通过比较相对非线性度的大小来选择汉明重量区分函数.通过仿真验证和实测验证,证明采用该方法能够正确地选择攻击效果较好的汉明重量区分函数.     

5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS

Voltage supply scaling in CMOS processes requires lower inductance and higher capacitance in conventional LC oscillators. Forcing several LC oscillators to run in phase is a valuable means of achieving the wanted phase noise with practical values of inductances and capacitances. However, in-phase oscillator arrays suffer from the up-conversion of transistors' flicker noise, in the presence of oscillator mismatches. A multitank oscillator topology is proposed, which has superior tolerance to mismatches and removes this mechanism of noise degradation. In order to assess such topology, an 802.11 a-compliant VCO with four coupled oscillators has been designed in a 0.13-mum CMOS technology. A phase noise better than -120 dBc/Hz at 1-MHz offset has been achieved along the 4.7-5.9-GHz tuning range     

Internet/Intranet系统设计中的安全对策

本文对网络安全进行技术分析，从不同角度阐述网络安全的隐患，在设计中采用相应对策，确保Internet/Intranet网络安全运行。     

A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-$mu$m CMOS

This paper describes a 3-tap finite impulse response programmable analog filter in 0.18-$muhbox m$CMOS. The filter is intended for polarization-mode dispersion compensation in 40-Gb/s long-haul single-mode optical fiber links. A novel filter topology is employed, whereby each tap gain comprises a cascade of two distributed amplifiers with adjustable gain. The same lumped LC ladders that provide the 25-ps tap delays also serve as artificial transmission lines for the distributed tap amplifiers. The prototype is 1 mm$times$1 mm ($hbox900 muhbox mtimes hbox600 muhbox m$active area) and consumes up to 70 mW from a 1.8-V supply depending on the tap gains. Linear equalization is demonstrated over a channel with 17 dB of loss at 20 GHz. A 50 mV per side eye amplitude with 14 dB signal-to-noise ratio is demonstrated at 30 Gb/s, and a modest 39 mV per side eye amplitude with 10 dB signal-to-noise ratio is achieved at 40 Gb/s.     

40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-μm CMOS

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.     

A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 $mu$m CMOS Technology

By combining an appropriate differential-sensing scheme with the bootstrapping technique, this paper presents a self-compensated design topology which is shown to be effective at reducing the loading effects due to the photodiode and the ESD protection circuit at the differential inputs. The built-in offset creation technique is introduced to overcome voltage headroom limitation. Furthermore, the negative impedance compensation is employed to enhance the gain-bandwidth product. The IC is shown to be tolerant of ESD protection circuit with 0.5 pF equivalent capacitance at the differential inputs. While connected to an InGaAs PIN photodiode exhibiting 0.8 pF equivalent capacitance, the implemented IC has achieved a differential transimpedance gain of 3.5 kOmega and a -3 dB bandwidth of 1.72 GHz. At a data rate of 3 Gb/s, the measured dynamic range is from -20 dBm to +0 dBm at a bit-error rate of 10^-12 with a 2³¹ -1 pseudorandom test pattern. The negative impedance compensation is shown to achieve enhancement factors of 4.5 dB and 520%, respectively, for transimpedance gain and - 3 dB bandwidth. The IC totally consumes 40 mW from a 1.8 V supply.     

Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter

Alpha particles, neutrons and laser-beam test results on an integrated pulse width modulation (PWM) controller operating in a DC/DC converter are presented in this paper. The PWM is fabricated on a 600-nm Bi-CMOS technology. Single-Event Transient (SET) derived from a bandgap circuit was amplified by a filter capacitor in the propagation path. Finally, a constant 6-??s SET pulse was observed on PGOOD pin which is a supervisory signal. This glitch caused system resets. Pulsed laser technology was adopted to locate the origin of the SET. 3D TCAD and circuit simulation tools were used to analyze the root cause. System and circuit level hardening approaches to mitigate the SET are also presented.     

办公室WLAN网络安全问题分析

WLAN因具有灵活性强、移动性强、组网简单、易于扩展、低成本等优点,被越来越广泛应用在办公环境,但它也会带来一些安全问题。文章首先从安全角度简要介绍WLAN,然后分析了办公环境下WLAN的几个安全问题,并给出相应的对策和建议。