High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.     

SONOS-type flash memory using an HfO/sub 2/ as a charge trapping layer deposited by the sol-gel spin-coating method

In this letter, the authors fabricate the silicon-oxide-nitride-oxide-silicon (SONOS)-like memory using an HfO/sub 2/ as charge trapping layer deposited by a very simple sol-gel spin-coating method and 900 /spl deg/C 1-min rapid thermal annealing. They examine the quality of sol-gel HfO/sub 2/ charge trapping layer by X-ray photoemission spectroscopy, Id-Vg, charge retention, and endurance. The threshold voltage shift is 1.2 V for the sol-gel HfO/sub 2/ trapping layer. The sol-gel HfO/sub 2/ film can form a deep trap layer to trap electrons for the SONOS-like memory. Therefore, the sol-gel device exhibits the long charge retention time and good endurance performance. The charge retention time is 10/sup 4/ s with only 6% charge loss and long endurance program/erase cycles up to 10/sup 5/.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

Rapid thermal annealed InGaN/GaN flip-chip LEDs

Nitride-based flip-chip (FC) light-emitting diodes (LEDs) emitting at 465 nm with Ni transparent ohmic contact layers and Ag reflective mirrors were fabricated. With an incident light wavelength of 465 nm, it was found that transmittance of normalized 300/spl deg/C rapid thermal annealed (RTA) Ni(2.5 nm) was 93% while normalized reflectance of 300/spl deg/C RTA Ni(2.5 nm)/Ag(200 nm) was 92%. It was also found that 300/spl deg/C RTA Ni(2.5 nm) formed good ohmic contact on n/sup +/ short-period-superlattice structure with specific contact resistance of 7.8/spl times/10/sup -4/ /spl Omega//spl middot/cm/sup 2/. With 20-mA current injection, it was found that forward voltage and output power were 3.15 V and 16.2 mW for FC LED with 300/spl deg/C RTA Ni(2.5 nm)/Ag(200 nm). Furthermore, it was found that reliabilities of FC LEDs were good.     

Embedded ferroelectric memory technology with completely encapsulated hydrogen barrier structure

A 0.18-/spl mu/m system LSI embedded ferroelectric memory (FeRAM) operating at a very low voltage has been developed for the first time. The low-voltage operation has been attained by newly developed stacked ferroelectric capacitors completely encapsulated by hydrogen barriers, which enable us to eliminate hydrogen reduction of the ferroelectric thin film during the back end of the line process including FSG, tungsten CVD (W-CVD), and plasma CVD SiN (p-SiN) passivation. A fabricated 1-Mbit one-transistor one-capacitor SrBi/sub 2/(Ta/sub x/Nb/sub 1-x/)/sub 2/O/sub 9/ (SBTN)-based embedded FeRAM operates at a low voltage of 1.1 V and ensures the endurance cycles up to 10/sup 12/ at 85/spl deg/C and the data retention time up to 1000 h at 125/spl deg/C, which is the most promising for mass production of 0.18-/spl mu/m low-power system LSI-embedded FeRAM and beyond.     

Roughness-enhanced electroluminescence from metal oxide silicon tunneling diodes

An approximate two-order increase in magnitude in electroluminescence was observed for the metal-oxide-silicon tunneling diodes with oxide grown at 900/spl deg/C, as compared to 1000/spl deg/C. The X-ray reflectivity revealed that the oxide grown at 900/spl deg/C has rougher interface than that grown at 1000/spl deg/C. The role of interface roughness can be understood in a model composed of phonons and interface roughness. An external quantum efficiency of /spl sim/10/sup -6/ was obtained using Al electrodes.     

Effect of annealing on GaN-insulator interfaces characterized by metal-insulator-semiconductor capacitors

GaN metal-oxide-semiconductor (MOS) capacitors have been used to characterize the effect of annealing temperature and ambient on GaN-insulator interface properties. Silicon dioxide was deposited on n-type GaN at 900 /spl deg/C by low-pressure chemical vapor deposition and MOS capacitors were fabricated. The MOS capacitors were used to characterize the GaN-SiO/sub 2/ interface with a low interface-state density of 3 /spl times/ 10/sup 11/ cm/sup -2/eV/sup -1/ at 0.25 eV below the conduction band edge, even after annealing in N/sub 2/ at temperatures up to 1100 /spl deg/C; however, insulator properties were degraded by annealing in NO and NH/sub 3/ at 1100 /spl deg/C.     

High-power P-i-N diode with local lifetime control using palladium diffusion controlled by radiation defects

We demonstrate for the first time a high-power P-i-N diode with local lifetime control using palladium (Pd) diffusion. Low-temperature (600/spl deg/C-700/spl deg/C) diffusion of Pd is stimulated by radiation defects resulting from alpha-particle irradiation (/sup 4/He/sup 2+/: 10 MeV, 10/sup 12/ cm/sup -2/). The region of maximal radiation damage of Gaussian shape is decorated by substitutional Pd after diffusion from a palladium silicide surface layer through the P/sup +/--P region into the N-base close to the anode junction. Significantly lower leakage current compared to that of standard /sup 4/He/sup 2+/ irradiation and very good ruggedness under fast recovery (di/dt/spl ap/500 A//spl mu/s, V/sub R//spl ap/2 kV) is demonstrated for Pd diffusion at 600/spl deg/C.     

Enhancing leakage suppression in carbon-rich silicon junctions

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4/spl times/10/sup -13/ A//spl mu/m, which is much lower than that of 1050 /spl deg/C spike annealed Si junctions and well within the I/sub off/ requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 /spl mu/m exhibit an I/sub off/ reduction of /spl sim/ 10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec.     

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.     

Retention testing of MNOS LSI memories

User-oriented test methods for MNOS LSI memories with built-in test modes have been developed. Their application is demonstrated on the commercial ER3401 memory. The memory retention is evaluated in two cases-the static retention time in power-down or in stand-by and the read retention during repeated reading, i.e., the maximum number of read cycles. In the first case, the two loss mechanisms, tunneling and thermal excitation of stored charge are evaluated separately and their influence is combined. In the second case, the limiting mechanism is slow writing by the read signal. On bases of these investigations, a static retention time of 60 yr at 70/spl deg/C and 2 yr at 125/spl deg/C is predicted and a read retention of 3/spl times/10/SUP 11/ read cycles at 70/spl deg/C and 2/spl times/10/SUP 9/ cycles at 125/spl deg/C is found for the ER3401.     

Thermally stable Ge/Ag/Ni Ohmic contact for InAlAs/InGaAs/InP HEMTs

Excellent annealed ohmic contacts based on Ge/Ag/Ni metallization have been realized in a temperature range between 385 and 500/spl deg/C, with a minimum contact resistance of 0.06 /spl Omega//spl middot/mm and a specific contact resistivity of 2.62 /spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ obtained at an annealing temperature of 425/spl deg/C for 60 s in a rapid thermal annealing (RTA) system. Thermal storage tests at temperatures of 215 and 250/spl deg/C in a nitrogen ambient showed that the Ge/Ag/Ni based ohmic contacts with an overlay of Ti/Pt/Au had far superior thermal stabilities than the conventional annealed AuGe/Ni ohmic contacts for InAlAs/InGaAs high electron mobility transistors (HEMTs). During the storage test at 215/spl deg/C, the ohmic contacts showed no degradation after 200 h. At 250/spl deg/C, the contact resistance value of the Ge/Ag/Ni ohmic contact increased only to a value of 0.1 /spl Omega//spl middot/mm over a 250-h period. Depletion-mode HEMTs (D-HEMTs) with a gate length of 0.2 /spl mu/m fabricated using Ge/Ag/Ni ohmic contacts with an overlay of Ti/Pt/Au demonstrated excellent dc and RF characteristics.     

Characterization of the temperature sensitivity of gain and recombination mechanisms in 1.3-/spl mu/m AlGaInAs MQW lasers

The potential of 1.3-/spl mu/m AlGaInAs multiple quantum-well (MQW) laser diodes for uncooled operation in high-speed optical communication systems is experimentally evaluated by characterizing the temperature dependence of key parameters such as the threshold current, transparency current density, optical gain and carrier lifetime. Detailed measurements performed in the 20/spl deg/C-100/spl deg/C temperature range indicate a localized T/sub 0/ value of 68 K at 98/spl deg/C for a device with a 2.8 /spl mu/m ridge width and 700-/spl mu/m cavity length. The transparency current density is measured for temperatures from 20/spl deg/C to 60/spl deg/C and found to increase at a rate of 7.7 A/spl middot/cm/sup -2//spl middot/ /spl deg/C/sup -1/. Optical gain characterizations show that the peak modal gain at threshold is independent of temperature, whereas the differential gain decreases linearly with temperature at a rate of 3/spl times/10/sup -4/ A/sup -1//spl middot//spl deg/C/sup -1/. The differential carrier lifetime is determined from electrical impedance measurements and found to decrease with temperature. From the measured carrier lifetime we derive the monomolecular ( A), radiative (B), and nonradiative Auger (C) recombination coefficients and determine their temperature dependence in the 20/spl deg/C-80/spl deg/C range. Our study shows that A is temperature independent, B decreases with temperature, and C exhibits a less pronounced increase with temperature. The experimental observations are discussed and compared with theoretical predictions and measurements performed on other material systems.     

As/sup +/-implanted AlGaAs oxide-confined VCSEL with enhanced oxidation rate and high performance uniformity

We report the utilization of an As/sup +/-implanted AlGaAs region and regrowth method to enhance and control the wet thermal oxidation rate for 850-nm oxide-confined vertical-cavity surface-emitting laser (VCSEL). The oxidation rate of the As/sup +/-implanted device showed a four-fold increase over the nonimplanted one at the As/sup +/ dosage of 1/spl times/10/sup 16/ cm/sup -3/ and the oxidation temperature of 400/spl deg/C. 50 side-by-side As/sup +/-implanted oxide-confined VCSELs fabricated using the method achieved very uniform performance with a deviation in threshold current of /spl Delta/I/sub th//spl sim/0.2 mA and slope-efficiency of /spl Delta/S.E./spl sim/3%.     

Implantation and activation of high concentrations of boron in Germanium

There is renewed interest in the development of Ge-based devices. Implantation and dopant activation are critical process steps for future Ge devices fabrication. Boron is a common p-type dopant, which remarkably is active immediately after implantation in Ge at low doses. This paper examines the effect of increasing dose (i.e., 5/spl times/10/sup 13/-5/spl times/10/sup 16/ cm/sup -2/) and subsequent annealing (400/spl deg/C-800/spl deg/C for 3 h in nitrogen) on activation and diffusion of boron in Ge. Secondary ion mass spectrometry (SIMS), spreading resistance profiling (SRP), high resolution X-ray diffraction (HRXRD), Rutherford backscattering spectrometry (RBS), and nuclear reaction analysis (NRA) are used to characterize the implants before and after annealing. It is found that very high fractions of the boron dose (/spl sim/5%-55%) can be incorporated substitutionally immediately after implantation leading to very high hole concentrations, /spl ges/2/spl times/10/sup 20/ cm/sup -3/, deduced from SRP. Small increases in activation after annealing are observed, however, 100% activation is not indicated by either SRP or NRA. Negligible diffusion after annealing at either 400/spl deg/C or 600/spl deg/C for 3 h was, furthermore, observed.     

High-voltage regulation and process considerations for high-density 5 V-only E/SUP 2/PROM's

A high density 5-V-only HMOS 1 FLOTOX E/SUP 2/PROM technology has been developed using stepper lithography and dry etching techniques. A 1.5-/spl mu/m minimum feature size and 0.5-/spl mu/m registration result in a FLOTOX cell with an area of 270 /spl mu/m/SUP 2/. This represents a 50% reduction of the original cell size. Equivalent endurance (10K cycles) and data retention (10 years) have been obtained. Improved critical dimension control has increased the uniformity of the new cell within the array. Junction leakage has been reduced by using an extended low-temperature anneal cycle. Circuit techniques have been developed to ensure full temperature range (-55-125/spl deg/C) operation. A capacitive voltage divider in a feedback loop, an E/SUP 2/ trimmable voltage reference, and a switched-capacitor RC network are employed to produce a temperature-stable programming pulse with a rising edge time constant of ~ 600 /spl mu/s. The programming voltage can be trimmed with an accuracy of /spl plusmn/ 0.5 V over a typical range of 19-24 V in order to match the requirements of the array. 16K and 64K 5-V-only E/SUP 2/PROMs with die sizes of 128 /spl times/ 182 mil and 223 X 278 mil have been fabricated.     

A novel MONOS-type nonvolatile memory using high-/spl kappa/ dielectrics for improved data retention and programming speed

This paper presents a novel metal-oxide-nitride-oxide-silicon (MONOS)-type nonvolatile memory structure using hafnium oxide (HfO/sub 2/) as tunneling and blocking layer and tantalum pentoxide (Ta/sub 2/O/sub 5/) as the charge trapping layer. The superiorities of such devices to traditional SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/ stack devices in obtaining a better tradeoff between faster programming and better retention are illustrated based on a band engineering analysis. The experimental results demonstrate that the fabricated devices can be programmed as fast as 1 /spl mu/s and erased from 10 ns at an 8-V gate bias. The retention decay rate of this device is improved by a factor more than three as compared to the conventional MONOS/SONOS type devices. Excellent endurance and read disturb performance are also demonstrated.     

A single-sided PHINES SONOS memory featuring high-speed and low-power applications

A single-sided PHINES SONOS memory with hot-hole injection in program operation and Fowler-Nordheim (FN) tunneling in erase operation has been demonstrated for high program speed and low power applications. High programming speed (/spl Delta/V/sub t//program time) of 5 V/20 /spl mu/s, low power consumption of P/E, high endurance of 10 K, good retention, and scaling capability can be demonstrated.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

Anodic Oxidation of Si in Oxygen/Chlorine Plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO/sub 2/ interface was reduced from 7 X 10/sup 11//cm/sup 2//spl dot/eV to 5 X 10/sup 11//cm/sup 2/ /spl dot/eV at the midgap of Si; after annealing at 800/spl deg/C in argon for 60 min, it was reduced to 8 X 10/sup 10//cm/sup 2//spl dot/eV, and did not return to the original value after heating the specimen to 800/spl deg/C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasma-anodic SiO/sub 2/ films was reduced by annealing them at 800/spl deg/C in argon, but SiO/sub 2/ films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.