The benefits of fluorine in pnp polysilicon emitter bipolartransistors

BF₂ implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is commonly used for the fabrication of pnp polysilicon emitter bipolar transistors. In this paper the effect of the fluorine, which is introduced into the polysilicon during the BF₂ implant, is investigated. Pnp polysilicon emitter bipolar transistors are fabricated in which the boron and fluorine are implanted separately, with the fluorine only going into one half of each wafer. Electrical results show that fluorine has two interrelated effects. In devices given a low thermal budget emitter drive-in, a drop in base current by a factor of approximately 3.2 is observed when the fluorine is present, together with an improvement in the ideality of the base characteristics. This is explained by the passivation of trapping states at the polysilicon/silicon interface by the fluorine. In contrast, in devices-given a higher thermal budget emitter drive-in, an increase in base current by a factor of approximately 2.5 is observed, when fluorine is present. This is explained by the action of the fluorine in accelerating the breakup of the interfacial layer. A model is proposed to explain this behavior     

The use of an interface anneal to control the base current andemitter resistance of p-n-p polysilicon emitter bipolar transistors

The effects of an interface anneal on the electrical characteristics of p-n-p polysilicon-emitter bipolar transistors are reported. For devices with a deliberately grown interfacial oxide layer, an interface anneal at 1100°C leads to a factor of 15 increase in base current, and a factor of 2.5 decrease in emitter resistance, compared with an unannealed control device. These results are compared with identical interface anneals performed on n-p-n devices, and it is shown that the increase in base current for p-n-p devices is considerably smaller than that for the n-p-n devices. This result is explained by the presence of fluorine in the p-n-p devices, which accelerates the breakup of the interfacial layer     

Effects of dislocations in silicon transistors with implanted emitters

Silicon bipolar transistors have been made by substituting a shallow phosphorus implanation for the standard emitter deposition used in the manufacture of linear integrated circuits. The implantation was followed by a high temperature heat treatment (drive-in), which caused the implanted ions to diffuse deeper into the semiconductor to give emitter/base junction depths of typically 1.8 μm. When the high temperature heat treatment was performed in an oxidising atmosphere, the resulting transistors had lower gains and higher emitter/base leakages than the comparable standard diffused transistors. However, if an 1180°C drive-in, in an inert atmosphere, was performed prior to the oxidation drive-in, high gains and low emitter/base leakages were obtained. Alternatively, if the oxidation drive-in was omitted, and instead an inert drive-in performed at any temperature between 1000 and 1180°C, high gains and low emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were caused by emitter edge dislocations intersection the emitter/base junction around the perimeter of the emitter. A mechanism is suggested to describe the formation of the emitter edge dislocations.     

Identification of a corner tunneling current component in advancedCMOS-compatible bipolar transistors

A corner tunneling current component in the reverse-biased emitter-base junction of advanced CMOS compatible polysilicon self-aligned bipolar transistors has been identified by measuring base current as a function of temperature, bias voltage, and emitter shape. This current is found to be an excess tunneling current caused by an increase in defect density in the corners of the emitter and gives rise to three-dimensional effects in small-geometry devices. The devices used for this study were selected from batches aimed at optimizing the emitter-base system. For this reason, the starting material was n-type (~10¹⁶ cm^-3) and provided the collector regions of the transistors. The intrinsic base and lightly doped extrinsic base regions were both implanted at 30 keV to a dose of 1×10¹³ cm^-2. The activation anneal was performed at 1060°C for 20 s in a rapid thermal annealer. Under such conditions, the emitter-base junction is located about 600 Å below the polysilicon-substrate interface     

Ion-implanted semiconductor devices

Ion implantation is finding increased usage in device fabrication owing to precise control and reproducibility of the charge and depth distribution of the implanted-dopant profile. The MOST illustrates the application of charge control through threshold-voltage adjustment and though predepostion for drive-in diffusion to form complementary devices. A compilation of range-energy data for B, P, and As in silicon is given along with factors which influence the implanted-dopant distributions after anneal treatments. Implantation procedures are presented for high-frequency bipolar transistors which depend critically on both charge and depth control of the emitter and base profiles. Another important aspect of ion implantation is lateral control, a feature which is necessary for high packing density circuits. Disorder effects associated with implantation through oxide masks are discussed. A brief account of implantation for GaAs devices is also included.     

Trade-off between emitter resistance and current gain inpolysilicon emitter bipolar transistors with intentionally growninterfacial oxide layers

Experimental measurements of emitter resistance and current gain in polysilicon emitter bipolar transistors that have received annealing to break up an intentionally grown RCA oxide interfacial layer are presented. An anneal of 900°C for 10 min in a nitrogen ambient of the interfacial layer prior to polysilicon doping resulted in a decrease in emitter resistance by approximately a factor of 5, with an increase in base saturation current of only 25% while still maintaining a current gain of around 500. The authors believe that this is the largest trade-off in emitter resistance versus current gain demonstrated so far for polysilicon transistors with an RCA interfacial layer. These results support a theory previously proposed by the authors (1991) predicting that significant trade-offs between emitter resistance and current gain can be obtained if an intentionally grown interfacial oxide layer in polysilicon emitter bipolar transistors is annealed so as to induce only partial breakup such that most of the layer remains intact     

On the perimeter base leakage of double-poly self-aligned p-n-ptransistors

It is shown that in the shallow junction formation for high-performance p-n-p devices, the perimeter E-B junction may be positioned inside the polysilicon due to insufficient boron dopants, causing excessive low-level base leakage current and current gain degradation. The I-V characteristic has an exp(qV /2kT) dependence consistent with carrier recombination at grain boundaries. Although the problem can be cured by using a deep emitter drive-in, the resulting AC performance will be traded off due to increased emitter charge storage. The nonuniform lateral profile limits the minimum achievable emitter junction depth for useful p-n-p devices, which in turn makes thin-base formation more difficult     

Revised method for extraction of the thermal resistance applied to bulk and SOI SiGe HBTs

A revision is presented of the technique to determine the junction temperature and thermal resistance of bipolar transistors. It is based on the temperature sensitivity of the base-emitter voltage when biasing the device under constant emitter current. It accounts correctly for the self-heating of the device during the measurement. Results are obtained for devices fabricated on silicon-on-insulator (SOI) and bulk silicon having different emitter widths and lengths. An increment of the thermal resistance is found for SOI devices with respect to bulk.     

Analysis and minimization of small-geometry effects on the currentgain of self-aligned `etched-polysilicon' emitter bipolar transistors

The authors report on a detailed analysis of small-geometry effects on the current gain of advanced self-aligned etched-polysilicon emitter bipolar transistors. By studying the dependence of collector and base currents on device geometry and process parameters, they have been able to identify the critical fabrication steps and physical mechanisms involved. The narrow emitter effect is caused by the butting of the emitter-base junction to the field oxide, and is mainly controlled by the gate oxide removal step prior to polysilicon deposition. Short emitter effects are associated with phenomena taking place in the spacer region of the device perimeter during polysilicon patterning, spacer pedestal thermal oxidation, link base implantation, and final rapid thermal anneal. Proper adjustment of all process parameters is shown to allow good control of the narrow-emitter effect and complete compensation of short-emitter effects, showing promise for the future of this CMOS-compatible bipolar transistor structure     

High-gain SOI polysilicon emitter transistors

The authors report the first high-gain polysilicon emitter bipolar transistors fabricated on zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) material. Current gains as high as 230 were obtained. Polysilicon emitter bipolar transistors made on bulk silicon wafers with identical and simultaneous heat treatments show significant differences in emitter resistance and DC characteristics as compared with SOI bipolar transistors. Post-metal anneal improves the current gain and base current ideality at low base-emitter voltages for both types of wafers     

Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

Comparison of one- and two-dimensional models of transistor thermal instability

The IC-VCElocus predicted by a one-dimensional model of thermal instability is compared with the IC-VCElocus predicted by a numerical model which accounts for nonuniform heat generation over the transistor area and also two-dimensional heat flow within the heat sink. Both models include the effects of distributed emitter and base ballast resistance, as well as the magnitude and temperature dependence of current gain. An important result obtained from this comparison is that the I-V loci predicted by the two models are very nearly the same, even though the temperature and power density profiles over the transistor die are distinctly different. It is the I-V locus which is of most practical interest, since it is one portion of the boundary of the forward safe operating area (SOA). The similarity of the I-V loci should allow one to use the simple one-dimensional model to predict a particular SOA, even though the assumptions under which the model was originally derived are not valid at the onset of thermal instability. Confirmation of this approach has been obtained by demonstrating good agreement between the measured safe operating area and that predicted by the one-dimensional model for both single- and double-diffused transistors. The predicted improvement due to the addition of discrete emitter resistors has also been verified by SOA measurements on actual devices. The device parameters which are important in determining SOA are the effective emitter and base resistances, the magnitude and temperature dependence of current gain, and the effective thermal resistance between the active region of the transistor and its heat sink. The quantitative dependence of SOA due to each of these parameters is described.     

Analytical modeling of oxide breakup effect on base current in n+-polysilicon emitter bipolar devices

The authors have modeled the base current change with different percentages of broken interface-oxide area (interface void). A pseudo-two-dimensional structure of dual channels of minority-carrier transport at the interface between the polysilicon and the silicon emitter, is constructed in analogy with an electrically equivalent conductance network. Using the conductance network, an analytical expression of base current is easily derived. For typical polysilicon emitter devices of ~10-15 Å interface oxide, the experimental results show that the strong dependence of base current on the fraction of interface void can be modeled. The simulation predicts that the base current will be insensitive to the fraction of interface oxide breakup for very thin interface-oxide polysilicon emitter devices. Recent reports on finding a process window between current gain and emitter resistance optimization in a certain range of interface breakup ratios are confirmed by the model     

Effects of dislocations in silicon transistors with implanted bases

Silicon bipolar transistors have been made by substituting a shallow boron implantation for the standard base deposition used in the manufacture of integrated circuits. This was followed by a high-temperature oxidation drive-in, and the transistor structure completed with a standard phosphorus deposition and drive-in. The implantations were performed through oxides with thicknesses in the range 0.08–0.17 μm. For the 0.17 μm transistors, the electrical characteristics were comparable with standard diffused transistors, while for the 0.08 μm transistors low gains and high emitter/base and collector/base leakages were obtained. For the latter transistors, etching and TEM studies revealed a dislocation network in the emitter region with a small fraction (10^?3) of the dislocations looping down to intersect the emitter/base and collector/base junctions. The poor electrical characteristics are explained in terms of the looping dislocations, and a mechanism is suggested to describe how the dislocations form.     

Comprehensive study of rapid, low-cost silicon surface passivationtechnologies

A comprehensive and systematic investigation of low-cost surface passivation technologies is presented for achieving high-performance silicon devices such as solar cells. Most commercial solar cells today lack adequate surface passivation, while laboratory cells use conventional furnace oxides (CFO) for high-quality surface passivation involving an expensive and lengthy high-temperature step. This investigation tries to bridge the gap between commercial and laboratory cells by providing fast, low-cost methods for effective surface passivation. This paper demonstrates for the first time, the efficacy of TiO₂, thin (<10 nm) rapid thermal oxide (RTO), and PECVD SiN individually and in combination for (phosphorus diffused) emitter and (undiffused) back surface passivation. The effects of emitter sheet resistance, surface texture, and three different SiN depositions (two direct PECVD systems and one remote plasma system) were investigated. The effects of post-growth/deposition treatments such as forming gas anneal (FGA) and firing of screen printed contacts were also examined. This study reveals that the optimum passivation scheme consisting of a thin RTO with a SiN cap followed by a very short 730°C anneal can 1) reduce the emitter saturation current density, J_0e, by a factor of >15 for a 90 Ω/sq. emitter, 2) reduce J_0e by a factor of >3 for a 40 Ω/sq, emitter, and 3) reduce S_back below 20 cm/s on 1.3 Ωcm p-Si. Furthermore, this double-layer RTO+SiN passivation is relatively independent of the deposition conditions (direct or remote) of the SiN film and is more stable under heat treatment than SiN or RTO alone. Model calculations are also performed to show that the RTO+SiN surface passivation scheme may lead to 17%-efficient thin screen-printed cells even with a low bulk lifetime of 20 μs     

A 1-μm polysilicon self-aligning bipolar process for low-powerhigh-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1-μm lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f_T =14 GHz at V_BC=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0×2.0 μm² a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz     

High-temperature DC characteristics of AlxGa0.52-xIn0.48P/GaAs heterojunction bipolar transistors grownby metal organic vapor phase epitaxy

A series of Al_xGa_0.52-xIn_0.48P/GaAs heterojunction bipolar transistors (HBT's) with x=0 to x=0.52 showed ideality factors close to unity for both base current and collector current and small variation in gain with temperature up to at least T=623 K across the whole range of x composition. Hole current injection from the base into the emitter in these devices was shown to be negligible. The current gain, β, which is temperature insensitive was thought to be limited by bulk base recombination for x⩽0.3 and recombination at the graded emitter region for x>0.3. The optimum emitter composition (highest β, and good β stability with collector current and temperature) was found to be x=0.18-0.30. Useful transistor action with very high gain and output resistance is possible up to at least T=623 K, limited only by the thermal performance of the unoptimized ohmic contacts employed in the devices     

Current gain and transit-time effects in HBTs with graded emitterand base regions

Two-dimensional simulations of the combined effects of emitter and base grading on the current gain and cutoff frequency f_t of heterojunction bipolar transistor (HBT) devices are presented. At low bias, the highest current gain was found to be obtained with an abrupt emitter and reduced by base grading, with f_t proportional to the collector current. At high bias, current gain was found to be enhanced by emitter grading, while base grading was found to reduce current gain if without emitter grading. Anticipated grading effects of lower band spikes and base transit time are found to be greatly modified by the changes of carrier density, lifetime, diffusion potential, and series resistance with bandgap     

Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors

This paper presents a detailed comparison of the measured and computed electrical characteristics of polysilicon emitter bi-polar transistors over a wide range of processing conditions. Detailed electrical measurements are made of both the emitter resistance and the base and collector current as a function of base-emitter voltage. Devices with arsenic- and phosphorus-doped emitters are considered, as well as both with and without a deliberately grown interfacial oxide layer. The theoretical characteristics are computed using a unified model that incorporates both transport and tunneling mechanisms. It is shown that the measured emitter resistances across a wide range of processing conditions can be satisfactorily explained using a tunneling model with a single value for the electron effective barrier height (0.4 eV). Values for the modeling parameters are obtained, in some cases uniquely by measurement, and in others by fitting the experimental results. In devices with a deliberately grown interfacial oxide, the base current is suppressed to such an extent that recombination in the single-crystal emitter and in the base becomes important.     

Double-step annealing and ambient effects on phosphorus implanted emitters in silicon

Emitters of npn silicon bipolar transistors have been made by a phosphorus implantation at 50 keV P⁺ to a dose of 1×10¹⁶ cm^?2. This was followed by high temperature processes to reduce lattice disorder, to drive-in the phosphorus atoms, and to form oxide layers. The first process step was carried out by using single- and double-step anneals in various ambients (dry N₂, dry O₂ and steam) while the drive-in and oxidation steps were common for all structures. Electrical measurements on emitter/base leakage current, low frequency (popcorn) noise and current gain showed that the annealing ambient had a major influence. The transistors with implanted emitters annealed in a dry N₂ ambient are comparable to commercial ones with thermally-diffused emitters. TEM observations on samples annealed in steam ambients revealed dislocatons extending into the sidewall of the emitter/base junction. This sidewall penetration of dislocations is the main origin of the degradation of the emitter/base junction characteristics.