fmax为30.8GHz的超薄Al2O3绝缘栅GaN MOS-HEMT器件

报道了一种利用原子层淀积(ALD)生长超薄(3.5nm)Al2O3为栅介质的高性能AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT).新型AlGaN/GaN MOS-HEMT器件栅长1μm,栅宽120μm,栅压为 3.0V时最大饱和输出电流达到720mA/mm,最大跨导达到130mS/mm,开启电压保持在-5.0V,特征频率和最高振荡频率分别为10.1和30.8GHz.     

f_(max)为30.8GHz的超薄Al_2O_3绝缘栅GaN MOS-HEMT器件(英文)

报道了一种利用原子层淀积(ALD)生长超薄(3.5nm)Al2O3为栅介质的高性能AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT).新型AlGaN/GaNMOS-HEMT器件栅长1μm,栅宽120μm,栅压为 3.0V时最大饱和输出电流达到720mA/mm,最大跨导达到130mS/mm,开启电压保持在-5.0V,特征频率和最高振荡频率分别为10.1和30.8GHz.     

fmax为30.8GHz的超薄Al2O3绝缘栅GaN MOS-HEMT器件

报道了一种利用原子层淀积(ALD)生长超薄(3.5nm)Al2O3为栅介质的高性能AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT).新型AlGaN/GaN MOS-HEMT器件栅长1μm,栅宽120μm,栅压为+3.0V时最大饱和输出电流达到720mA/mm,最大跨导达到130mS/mm,开启电压保持在-5.0V,特征频率和最高振荡频率分别为10.1和30.8GHz.     

AlGaN/GaN异质结场效应晶体管的阈值电压

利用AlGaN/GaN异质结场效应晶体管(AlGaN/GaN HFET)栅结构的电容-电压(C-V)特性确定AlGaN/GaN HFET的阈值电压.通过对模拟计算得到的AlGaN/GaN HFET电流-电压(I-V)特性曲线与测试得到的AlGaN/GaN HFET曲线比较分析,证实了依据AlGaN/GaN HFET栅结构的C-V特性曲线的微分极值点确定阈值电压是一种切实可行的方法.     

AlGaN/GaN异质结场效应晶体管的阈值电压

利用AlGaN/GaN异质结场效应晶体管(AlGaN/GaN HFET)栅结构的电容-电压(C-V)特性确定AlGaN/GaN HFET的阈值电压.通过对模拟计算得到的AlGaN/GaN HFET电流-电压(I-V)特性曲线与测试得到的AlGaN/GaN HFET曲线比较分析,证实了依据AlGaN/GaN HFET栅结构的C-V特性曲线的微分极值点确定阈值电压是一种切实可行的方法.     

基于SiC基底的Y2O3/Al2O3堆栈MOS 电容的特性研究

通过在n型碳化硅(SiC)晶圆上用物理气相沉积法(PVD)和原子层沉积法(ALD)分别沉积 Y2O3介质和Al2O3，形成金属/Al2O3/Y2O3/SiC高k介质堆栈结构MOS电容，X射线光电子能谱(XPS)分析研究Al2O3/Y2O3堆栈结构氧化层介质之间以及氧化层与SiC晶圆之间的相互扩散和反应关系，研究不同金属电极MOS电容的C-V特性，Ni电极MOS电容具有良好的稳定性，对介质层的相对介电常数影响最小，Mg电极MOS电容的理想平带电压最小，同时氧化层陷阱密度最小，随着C-V测试频率的降低，氧化层电容Cox逐渐增加Al2O3/Y2O3介质层的相对介电常数逐渐增大，等效氧化层厚度(EOT)减小，平带电容电压减小。     

AlGaN/GaN HFET的2DEG和电流崩塌研究(Ⅰ)

从不同的视角回顾和研究了A1GaN/GaN HFET的二维电子气(2DEG)和电流崩塌问题.阐述了非掺杂的AIGaN/GaN异质结界面存在2DEG的原动力是极化效应,电子来源是AlGaN上的施主表面态.2DEG浓度与AlGaN/GaN界面导带不连续性、AlGaN层厚和Al组分有密切关系.揭示了AlGaN/GaN HFET的2DEG电荷涨落受控于表面、界面和缓冲层中的各种缺陷及外加应力,表面空穴陷阱形成的虚栅对输入信号有旁路和延迟作用,它们导致高频及微波状态下的电流崩塌.指出由于构成电流崩塌因素的复杂性,各种不同的抑制电流崩塌方法都存在不足,因此实现该器件大功率密度和高可靠性还有很长的路要走.     

高阈值电压低界面态增强型Al2O3/GaN MIS-HEMT

采用高温热氧化栅极凹槽刻蚀工艺并结合高温氮气氛围退火技术,制备出了高阈值电压的硅基GaN增强型Al_2O_3/GaN金属-绝缘体-半导体高电子迁移率晶体管(MIS-HEMT)。采用高温热氧化栅极凹槽刻蚀工艺刻蚀AlGaN层,并在AlGaN/GaN界面处自动终止刻蚀,可有效控制刻蚀的精度并降低栅槽表面的粗糙度。同时,利用高温氮气退火技术能够修复Al_2O_3/GaN界面的界面陷阱,并降低Al_2O_3栅介质体缺陷,因此能够减少Al_2O_3/GaN界面的界面态密度并提升栅极击穿电压。采用这两项技术制备的硅基GaN增强型Al_2O_3/GaN MIS-HEMT具有较低的栅槽表面平均粗糙度(0.24 nm)、较高的阈值电压(4.9 V)和栅极击穿电压(14.5 V)以及较低的界面态密度(8.49×10¹¹ cm^-2)。     

RF-MBE生长的高Al势垒层AlGaN/GaN HEMT结构

采用RF-MBE技术,在蓝宝石衬底上生长了高Al组分势垒层AlGaN/GaN HEMT结构.用三晶X射线衍射分析得到AlGaN势垒层的Al组分约为43%,异质结构晶体质量较高,界面比较光滑.变温霍尔测量显示此结构具有良好的电学性能,室温时电子迁移率和电子浓度分别高达1246cm2/(V·s)和1.429×1013cm-2,二者的乘积为1.8×1016V-1·s-1.用此材料研制的器件,直流特性得到了提高,最大漏极输出电流为1.0A/mm,非本征跨导为218mS/mm.结果表明,提高AlGaN势垒层Al的组分有助于提高AlGaN/GaN HEMT结构材料的电学性能和器件性能.     

双异质外延SOI材料Si/γ-Al_2O_3/Si的外延生长

利用MOCVD(metalorganic chemical vapor deposition)和APCVD(atmosphere chemical vapor deposition)硅外延技术在Si(10 0 )衬底上成功地制备了双异质Si/γ- Al2 O3/Si SOI材料.利用反射式高能电子衍射(RHEED)、X射线衍射(XRD)及俄歇能谱(AES)对材料进行了表征.测试结果表明,外延生长的γ- Al2 O3和Si薄膜都是单晶薄膜,其结晶取向为(10 0 )方向,外延层中Al与O化学配比为2∶3.同时,γ- Al2 O3外延层具有良好的绝缘性能,其介电常数为8.3,击穿场强为2 .5 MV/cm.AES的结果表明,Si/γ- Al2 O3/Si双异质外延SOI材料两个异质界面陡峭清晰.     

Gate-First AlGaN/GaN HEMT Technology for High-Frequency Applications

This letter describes a gate-first AlGaN/GaN high-electron mobility transistor (HEMT) with a W/high- $k$ dielectric gate stack. In this new fabrication technology, the gate stack is deposited before the ohmic contacts, and it is optimized to stand the 870 $^{circ}hbox{C}$ ohmic contact annealing. The deposition of the W/high-$k$ dielectric protects the intrinsic transistor early in the fabrication process. Three different gate stacks were studied: $hbox{W}/ hbox{HfO}_{2}$, $hbox{W}/hbox{Al}_{2}hbox{O}_{3}$ , and $hbox{W}/hbox{HfO}_{2}/hbox{Ga}_{2}hbox{O}_{3}$ . DC characterization showed transconductances of up to 215 mS/mm, maximum drain current densities of up to 960 mA/mm, and more than five orders of magnitude lower gate leakage current than in the conventional gate-last Ni/Au/Ni gate HEMTs. Capacitance–voltage measurements and pulsed-$IV$ characterization show no hysteresis for the $hbox{W}/hbox{HfO}_{2}/ hbox{Ga}_{2}hbox{O}_{3}$ capacitors and low interface traps. These W/high- $k$ dielectric gates are an enabling technology for self-aligned AlGaN/GaN HEMTs, where the gate contact acts as a hard mask to the ohmic deposition.      

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Recessed 70-nm Gate-Length AlGaN/GaN HEMTs Fabricated Using an $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Dielectric Layer

In this letter, a novel process for recessed-gate AlGaN/GaN high-electron-mobility transistors using an $hbox{Al}_{2}hbox{O}_{3}/ hbox{SiN}_{x}$ dielectric has been developed. The $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ dielectric bilayer was used as a recess etch-mask for short-gate-footprint definition. Recessed-gate devices with a gate length of 70 nm have been fabricated on a molecular-beam-epitaxy-grown layer structure using this process. After the removal of the dielectric layers, excellent dc and small-signal results, a high drain–current density of 1.5 A/mm, a unity gain cutoff frequency of 160 GHz, and a maximum frequency of oscillation of 200 GHz were obtained.      

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.     

钝化前表面预处理对AlGaN/GaN HEMTs性能的影响

提出一种新的钝化技术--采用盐酸和氢氟酸混合预处理溶液(HF:HCI:H2O=1:4:20)对AIGaN/GaNHEMTs进行表面预处理后冉淀积Si3N4钝化,研究了新型钝化技术对AlGaN/GaN HEMTs性能的影响并分析其机理.与用常规方法钝化的器件相比,经过表面顶处理再钝化,成功地抑制了 AIGaN/GaN HEMTs肖特基特性的恶化,有效地增强抑制电流崩塌效应的能力,将GaN基HEMTs的输出功率密度提高到5.2W/mm,并展现良好的电学可靠性.通过X射线光电子谱(XPS)检测预处理前后的AIGaN表面,观察到经过预处理后的AIGaN表面氧元素的含量大幅度下降.表面氧元素的含量下降,能有效地降低表面态密度和表面电荷陷阱密度,被认为是提高AIGaN/GaN HEMTs性能的主要原因.     

Effect of Fluoride‐based Plasma Treatment on the Performance of AlGaN/GaN MISHFET

This paper demonstrates the effect of fluoride‐based plasma treatment on the performance of Al₂O₃/AlGaN/GaN metal‐insulator‐semiconductor heterostructure field effect transistors (MISHFETs) with a T‐shaped gate length of 0.20 μm. For the fabrication of the MISHFET, an Al₂O₃ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using CF₄ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the Al₂O₃ gate dielectric layer to the plasma environment. The thickness of the Al₂O₃ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off‐state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.