变压器耦合LC正弦波振荡器的分析

在高频电子线路的教学中,变压器耦合反馈振荡器是LC正弦波振荡器中的重要内容。本文以常用的瞬时极性法分析了变压器耦合振荡电路的相位起振条件,以环路增益T的形式推导了振荡器的振幅起振条件,从而清晰地阐述了振荡器的工作原理,振幅起振条件及振荡频率与电路中各参数的关系。     

振荡器谐振回路的参数选择

针对振荡器谐振回路参数的选择较多地依赖于经验的问题,提出了从振荡器的等效电路出发,得到了描述振荡器的非线性微分方程,通过引入随机项来描述振荡器的内部电噪声,由此建立了用于分析振荡器行为的非线性随机微分方程。并针对遗传算法对振荡器谐振回路参数的优选结果,采用10MHz的Pierce晶体振荡器,得出了实证依据。当C1和C2比较接近时,Pierce振荡电路中的相位噪声可得到更好的抑止。     

不同类型噪声作用下振荡器的相位噪声分析

相位噪声是振荡器最重要的性能指标.文中从描述振荡器的非线性微分方程出发,提出将噪声作为非线性微分方程的一项,通过建立随机非线性微分方程来分析振荡器的相位噪声,为振荡器的相位噪声提出了一种新的分析方法.用这种方法,在相同强度下,针对白噪声分别为加性和乘性的情形,分析其产生的相位噪声,得出了乘性噪声产生的相位噪声远大于加性噪声所产生的相位噪声的结论.     

宽带LC压控振荡器的相位噪声优化设计

采用0.35 μm BiCMOS工艺,设计了一款基于开关电容阵列结构的宽带LC压控振荡器.同时分析了电路中关键参数对相位噪声的影响.基于对VCO中LC谐振回路品质因数的分析,优化了谐振回路,提高了谐振回路的品质因数以降低VCO的相位噪声.采用噪声滤波技术,减小了电流源晶体管噪声对压控振荡器相位噪声的影响.测试结果表明,优化后的压控振荡器能够覆盖1.96～2.70 GHz的带宽,频偏为100 kHz和1 MHz的相位噪声分别为-105和-128 dBc/Hz,满足了集成锁相环对压控振荡器的指标要求.     

环形压控振荡器的噪声分析

在振荡器的设计中,为了得到更高性能,分析其相位噪声是十分重要的.利用Razavi对具有普遍意义的品质因数的定义将Leeson针对LC振荡器提出的相位噪声模型应用到环形振荡器上对其进行噪声分析.文中以一个2 GHz环形振荡器为例,采用TSMC 0.25 μm CMOS工艺参数,用Cadence的spectre仿真器进行仿真.电源电压为2.5 V,偏离中心频率1 MHz处的相位噪声为-86.6 dBc/Hz.仿真的结果与噪声模型所的结果基本吻合.     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点.从LC振荡器的模型出发,研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响.给出了LC振荡器的设计要点及设计中需要考虑的约束条件.     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点.从LC振荡器的模型出发,研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响.给出了LC振荡器的设计要点及设计中需要考虑的约束条件.     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点. 从LC振荡器的模型出发，研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响. 给出了LC振荡器的设计要点及设计中需要考虑的约束条件.     

缓冲器输出端相位噪声模型分析

相位噪声是振荡器的重要性能指标。近年来,研究人员在振荡器相位噪声表征方面已经做了大量的工作,在这些过程中开发出了很多不同类型的振荡器相位噪声模型。但是在这些模型中,都没有分析缓冲器噪声对振荡器相位噪声的影响。而在研究课题中,首先要对缓冲器噪声的功率谱密度函数进行数学建模,并易于将这个模型嵌入到相位噪声的非线性扰动分析模型,这样就得到了含有缓冲器噪声的振荡器相位噪声模型。     

一种基于阻抗变换的低噪声LC压控振荡器设计

为了提高相位噪声性能，提出了一种基于阻抗变换模块的新型无尾电流源电感电容(LC)压控振荡器，该阻抗变换模块位于交叉耦合晶体管的漏极与栅极之间，能够减少有源器件产生的噪声，并且交叉耦合晶体管主要位于饱和区域，能够防止LC 谐振腔的品质因数降低。此外，相较于传统LC振荡器，该振荡器在低电压工作条件下能够维持低相位噪声性能，并采用0.18μｍ CMOS工艺进行了具体实现。实验结果表明:在3ＭＨｚ偏移频率的条件下，提出的振荡器相位噪声范围为-138.8ｄＢｃ / Ｈｚ~ -141.1ｄＢｃ/Ｈｚ，调谐范围增加了大约22.8％，在此调谐范围内，与其他提LC压控振荡器相比，所提方法具有更大的品质因数更，具体为191.8ｄＢｃ/Ｈｚ。     

CMOS LC-oscillator phase-noise analysis using nonlinear models

In this paper, a second-order stochastic differential equation is used as a tool for the analysis of phase noise in a submicron CMOS LC oscillator. A cross-coupled topology typical of integrated CMOS designs is considered. Nonlinear limiting and mobility degradation effects in the circuit are modeled and used to predict the statistics of the random amplitude and phase deviations in terms of design variables. Assuming Gaussian noise disturbances and describing the phase noise as a random diffusion process, the average phase-noise power spectrum is derived and its accuracy verified with measurement and simulation results. Calculations for phase noise arising from stationary tank noise, nonstationary channel thermal noise, and flicker noise are discussed. The analysis is used to emphasize the fundamental power/performance tradeoff associated with compensation of tank losses via adjustments in the power supply and device size.     

Design issues in CMOS differential LC oscillators

An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors     

Design of an Optimized 2.5 GHz CMOS Differential LC Oscillator with Nonlinear Analysis for MOS Varactor

The oscillation amplitude and supply current relations for a differential CMOS oscillator are derived by using an analytic method. A simplified model to predict the phase noise performance of the oscillator is developed. The large signal analysis of a nonlinear inversion mode MOS varactor is presented. The derived expressions can help to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the method has been verified by designing an LC CMOS oscillator in a 0.25 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.     

Technique for Flicker Noise Up-Conversion Suppression in Differential LC Oscillators

A novel technique for the suppression of the flicker noise up-conversion in a differential LC oscillator topology is proposed. Relaxation mechanism and tunable noise filtering of the relaxation thresholds provide simultaneous suppression of differential pair and bias transistor flicker noise contributions. The proposed technique is validated on a fully monolithic oscillator architecture and 0.35-mum standard CMOS process by Cadence SpectreRF for the frequency range of 2.9-5.9 GHz. The phase noise improvement at 10 kHz offset versus a single-differential-pair LC oscillator is 6-15 dB across the tuning range.     

Influence of noise intensity on the spectrum of an oscillator

This paper investigates the influence of high-intensity noise on the correlation spectrum of a two-dimensional (2-D) nonlinear oscillator. An exact analytical solution for the correlation spectrum of this 2-D oscillator is provided. The analytical derivations are well suited for oscillators with white noise of any intensity, but computational constraints on the solution of the partial differential equation may make it impractical for cases where the number of state variables exceeds three. The spectral results predicted by our analytical method are verified by numerical simulations of the noisy oscillator in the time domain. We find that the peak of the oscillator spectrum shifts toward higher frequencies as the noise intensity is increased, as opposed to the fixed oscillation frequency predicted in the existing literature. This phenomenon does not appear to have been reported previously in the context of phase noise in oscillators.     

Oscillator phase noise: a tutorial

Linear time-invariant (LTI) phase noise theories provide important qualitative design insights but are limited in their quantitative predictive power. Part of the difficulty is that device noise undergoes multiple frequency translations to become oscillator phase noise. A quantitative understanding of this process requires abandoning the principle of time invariance assumed in most older theories of phase noise. Fortunately, the noise-to-phase transfer function of oscillators is still linear, despite the existence of the nonlinearities necessary for amplitude stabilization. In addition to providing a quantitative reconciliation between theory and measurement, the time-varying phase noise model presented in this tutorial identifies the importance of symmetry in suppressing the upconversion of 1/f noise into close-in phase noise, and provides an explicit appreciation of cyclostationary effects and AM-PM conversion. These insights allow a reinterpretation of why the Colpitts oscillator exhibits good performance, and suggest new oscillator topologies. Tuned LC and ring oscillator circuit examples are presented to reinforce the theoretical considerations developed. Simulation issues and the accommodation of amplitude noise are considered in appendixes     

Phase Noise and Jitter in CMOS Ring Oscillators

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker ($1/f$) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.     

Full oscillation cycle phase noise analysis of differential CMOS LC oscillators

This paper analyzes the phase noise of the widely used differential LC oscillator topology and presents brief equations describing phase noise over the entire oscillation period. The findings show that if a capacitance is present at the source node of the differential pair, two phenomena occur that increase the phase noise: the switch time increases, lengthening the interval spent in a noisy balanced state and increasing the transistor noise excess factor; and at higher frequencies the unbalanced state starts to contribute phase noise. The analysis is based upon the superposition of piecewise linear equations using the EKV transistor model, which includes a concise formulation of the noise excess factor.