Novel c.c.d. signal integrator

The implementation of a c.c.d. signal integrator to improve the signal/clutter ratio of radar returns is described. A parallel-transfer scheme is employed, in which the effects of transfer inefficiency on performance are minimised. Preliminary investigations with a test device are reported.     

Influence of charge-transfer inefficiency on c.c.d. recursive-filter performance

A simple delay-element model is given to account for the charge-transfer inefficiency of c.c.d.s. The experimental and calculated frequency responses of a recursive filter are given to illustrate the suitability of the model.     

Modulation transfer function of quadrilinear c.c.d. imager

The influence of transfer inefficiency on the spatial resolution of linear c.c.d. imagers is discussed. For a new imager concept, the quadrilinear imager which was reported elsewhere, this m.t.f. is derived and compared with that of already known imagers.     

Adaptive cancellation of fixed-pattern noise in c.c.d. serial-parallel-serial memory

The letter addresses the problem of the effective implementation of long analogue delay lines. Charge-coupled devices (c.c.d.) appear attractive for this application but suffer from the problem of signal smearing due to imperfect charge transfer. Although s.p.s. delay-line configurations minimise charge-transfer inefficiency, they emphasise the significance of dark current which can cause severe fixed-pattern noise problems in this architecture. A scheme is proposed here for the cancellation of fixed-pattern noise in s.p.s. delay lines and results are presented to demonstrate the effectiveness of the system.     

Meander-channel c.c.d. (m.c.c.d.) recursive filter

A modified input-weighting concept for a c.c.d. recursive filter is proposed; it has been implemented using an m.c.c.d. with a complementary input scheme which provides net weighting coefficients. This improved structure requires neither operational amplifiers nor resistors. The operation and performance of the fabricated 2nd-order bandpass filter are presented.     

Meander channel c.c.d. (m.c.c.d.) transversal filter

A simple and compact m.c.c.d. transversal filter is presented. The device features (a) an input-weight technique to achieve a large output voltage, (b) a new `split-input-gate? weighting to provide accurate filter coefficients, and (c) a simplified electrode structure by using the m.c.c.d. as a summing register.     

A novel c.c.d. multiplying input technique

A useful technique for operating the I/P stages of a c.c.d. as a multiplier is described. Since the two multiplying inputs are applied to the input diffusion and input gate the method should be widely applicable to most c.c.d. structures.     

Minimal-transfer c.c.d. structures

Analogue c.c.d. storage arrays are limited by the transfers undergone by each information element. Topological constraints militate against large tree structures, with transfers proportional to only log (storage capacity). Nevertheless, with some emitter-follower interfaces, multiply-branching c.c.d. arrays can approach this limit. This could dramatically increase storage capacity for a given transfer efficiency.     

More active RC filters using the d.v.c.c.s./d.v.c.v.s.

Novel configurations using a differential-voltage-controlled current source, differential-voltage-controlled voltage source (d.v.c.c.s./d.v.c.v.s.) as the active building block are described. The configurations assume that the active building block is divided into two independent parts initially.     

Discrete cosine transform processor using a c.c.d. programmable transversal filter

The design and performance of a compact discrete-cosine prime-transform processor using a charge-coupled-device programmable transversal filter is reported. The c.c.d. design used here allows the required operations of data permutation and correlation to be performed in the same device. In addition, this arrangement permits an N-stage c.c.d. filter to be used for implementation of an N-point transform. This represents a factor-of-two reduction in c.c.d. stages over previously reported systems.     

Charge-splitting c.c.d. tapped delay lines

Two new types of c.c.d. tapped delay lines are described. One has parallel channels separated by channel stops from input to output. The other has channel stop wedges partitioning charge packets down the device. High performance is achieved.     

New c.c.d. programmable transversal filter

A c.c.d. transversal-filter structure is described which is capable of processing signals at high data rates. The tap weights can be programmed as digital words. A 32-stage prototype device has been tested at clock rates up to 20 MHz; operation at even higher data rates appears feasible.     

Coefficient correction in programmable c.c.d. recursive filters

A technique for correcting coefficient errors in c.c.d. recursive filters is described. The technique is demonstrated on a programmable second-order Chebyshev lowpass filter.     

Techniques for increasing the effective charge-transfer efficiency of tapped c.c.d. registers

A design technique for multitap c.c.d. delay lines is discussed in which the effective charge transfer efficiency is increased over its intrinsic process-dependent value. The technique involves locating tap amplifiers at every alternate bit, and operating the device at twice the normal clock rate. The advantages of the technique are discussed with reference to a 32-tap, n-channel c.c.d. delay line.     

Active RC bandpass and lowpass filters using the d.v.c.c.s./d.v.c.v.s.

A novel configuration using the differential voltage-controlled current source, differential voltage-controlled voltage source (d.v.c.c.s./d.v.c.v.s.) as the active building block is introduced. The realisations of bandpass and lowpass filters are given as special cases; both filters are canonic, and a moderate pole Q-factor can be obtained in each case.     

Analogue c.c.d. correlator using monolithic m.o.s.t. multipliers

A 32-stage analogue correlator has been hybridised by using a multitapped c.c.d. delay line and m.o.s.t. multipliers fabricated on the same silicon chip. A multiple-port sample?hold system has been adopted for storage of the reference signal, thereby allowing it to be refreshed continuously. The viability of a design for a fully analogue monolithic c.c.d. correlator is established.     

New charge-differencing technique for c.c.d. transversal filters

A new charge-differencing technique for use with c.c.d. transversal filters employing charge sensing is described. The method eliminates the need for a voltage-differencing amplifier and requires the addition of one extra matched capacitor.     

New ideal active inductance and frequency-dependant negative resistance using d.v.c.c.s./d.v.c.v.s.: applications in sinusoidal-oscillator realisation

A new grounded-capacitor simulation of driving-point impedances of the form as and bs2, corresponding to ideal inductance and frequency-dependent negative resistance (f.d.n.r.) elements, respectively, is presented. The configurations use the minimum of passive components with the d.v.c.c.s./d.v.c.v.s. as the active element. Applications of the active inductance and f.d.n.r. are then proposed in the realisation of some single-resistor-controlled RC oscillators.     

Spectrum analysis with a c.c.d. delay line

A novel form of c.c.d. spectrum analyser is described which functions by performing the discrete Fourier transform. The approach is based on the coherent-memory-filter principle and is well suited to Doppler processing. Results are given for a 10 kHz analyser with 200 Hz resolution.     

Step and frequency responses of c.t.d.s with nonuniform transfer inefficiency

General models for the small-signal step and frequency responses of charge-transfer devices with nonuniform inefficiency are derived. The case when the transfer inefficiency becomes position-dependent due to a nonuniform distribution of the background charge along the register is experimentally investigated using bucket-brigade delay lines as test vehicles.