A 2-D Semi-Analytical Model of Double-Gate Tunnel Field-Effect Transistor Xu Huifang (许会芳), Dai Yuehua*(代月花), Li Ning(李宁), Xu JianBin(徐建斌)

文中提出了一种双栅隧穿场效应晶体管(DG TFET)的二维半解析模型。通过在栅绝缘层和沟道区引入两个矩形源,运用半解析法和特征函数展开法求解二维泊松方程,得到电势的二维半解析解。解的结果是一个特殊函数,为无穷级数表达式。基于电势模型,求出最短隧穿长度( )和平均电场( ),运用Kane模型得到漏极电流。新模型考虑了移动电荷对电势的影响以及漏源电压对隧穿参数 和 的影响。文中计算了不同漏源电压,不同硅膜厚度,栅介质层厚度和栅介质层常数下的表面势和漏极电流。结果表明,新模型与仿真结果吻合。这将有助于DG TFET的优化设计,同时,也加深了DG TFET器件对电路结构设计的规划。     

Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs

A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor (Si-DG TFET) is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed (as in the case of the DG MOSFET); instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential (eQFP) decreases as the channel potential starts to decrease, and there are hiphops in the channel eQFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I-V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.     

非晶IGZO薄膜晶体管开启区电流的解析模型

对非晶In-Ga-Zn-Oxide薄膜晶体管,假设能隙中陷阱态密度呈指数分布,给出了解析的电流模型。运用薄层电荷近似的方法推导陷落电荷和自由电荷表达式,并基于此给出了基于表面势的电流表达式。在此电流表达式的基础上,通过泰勒展开,给出了基于阈值电压的电流表达式。基于表面势和基于阈值电压的电流表达式的计算结果与测量数据相比较,符合得很好。     

A closed-form trapped-charge-included drain current compact model for amorphous oxide semiconductor thin-film transistors

A closed-form drain current compact model for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), including the influence from trapped charges, is presented in this paper. Accounting for both channel and interface trapped charges in this model, we explicitly solve the inherent closed-form surface potential by improving the computational efficiency of the effective charge density approach. Furthermore, based on the explicit solution of the surface potential, the expressions of the trapped and inversion charges in the channel film are derived analytically, and the drain current is integrated from the charge sheet model. Then, for the cases of the different operational voltages, the accuracy and practicability of our model are verified by numerical results of the surface potential and experimental data of the drain current in amorphous In-Ga-Zn-O TFTs, respectively. Finally, we give a discussion about the influence of the interface trapped charges on the device reliability. As a result, the model can be easily to explore the drain current behavior of the AOS TFTs for next-generation display circuit application.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

Analytical drain current model for amorphous IGZO thin-film transistors in above-threshold regime

An analytical drain current model is presented for amorphous In-Ga-Zn-oxide thin-film transistors in the above-threshold regime,assuming an exponential trap states density within the bandgap.Using a charge sheet approximation,the trapped and free charge expressions are calculated,then the surface potential based drain current expression is developed.Moreover,threshold voltage based drain current expressions are presented using the Taylor expansion to the surface potential based drain current expression.The calculated results of the surface potential based and threshold voltage based drain current expressions are compared with experimental data and good agreements are achieved.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

基于陷落电荷效应的非晶硅TFT的开态电流模型

对非晶硅薄膜晶体管,提出基于陷落电荷和自由电荷分析的新方法。考虑到带隙中指数分布的深能态和带尾态,给出了基于阈值电压的开启区电流模型。定义阈值电压为栅氧/半导体界面处陷落于深能级陷阱态的电荷与陷落于带尾态的电荷相等时所对应的栅压。电流模型中,引入一陷落电荷参数β,此参数建立了电子的带迁移率与有效迁移率之间的关系。最后,将电流模型同时与Pao-Sah模型和实验数据进行比较和验证,结果表现出很好的一致性。     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

A theoretical model for the current-voltage characteristics of afloating-gate EEPROM cell

A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell     

A charge sheet model for MOSFETs with an abrupt retrograde channel Part I. Drain current and body charge

Analytical solutions to drain current, depletion and inversion charges for MOSFETs with an ideally abrupt retrograde doping profile in the channel are derived based on the charge sheet model. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations; the modeling and simulation results are in excellent agreement. It is shown that the inclusion of an intrinsic surface layer in the channel causes a voltage shift in the drain current, in accordance with experimental observations. For the depletion charge, an analytical expression principally identical to that for the uniformly doped body case is found with a simple replacement of the surface potential, ψ_s, by the potential at the interface between the intrinsic surface layer and the doped substrate, ψ_ξ.     

The threshold-voltage model of MOSFET devices with localizedinterface charge

A new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented. Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the two-dimensional (2-D) Poisson's equation. Calculating the minimum surface potential, the analytic threshold-voltage model is derived. It is verified that the model accurately predicts the threshold voltage for both fresh and damaged devices. Moreover, the Drain-Induced Barrier Lowering (DIBL) and substrate bias effects are included in this model. It is shown that the screening effects due to built-in potential and drain bias dominate the impact of the localized interface charge on the threshold voltage. Calculation results show that the extension, position and density of localized interface charge are the main issues influencing the threshold voltage of a damaged MOSFET device. Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreement is obtained for various cases     

Oxide-trap-induced instability of GIDL of thermally nitrided-oxideN-MOSFET's under stress

Some holes created from band-to-band (B-B) tunneling in the deep-depletion region of the drain can be injected into the gate oxide and reduce the vertical field there. As a result, gate-induced drain leakage (GIDL) current decreases. This kind of hot-hole injection depends on the voltage difference between the drain and gate, due to nitridation-induced lowering of the barrier height for hole injection at the SiO₂-Si interface. The subsequent hot-electron injection can neutralize these trapped holes, and make the GIDL current recover, and even increase beyond its original value. Since the trapped charges also affect the lateral field, the observed change in the ratio of substrate to source currents further confirms the proposed mechanism for the GIDL degradation and recovery behavior     

An analysis of the threshold voltage for short-channel IGFET''s

For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length.

The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.     

关态应力下P-MOSFETs的退化

研究了沟长从0.525μm到1.025μm 9nm厚的P-MOSFETs在关态应力(Vgs＝0,Vds＜0)下的热载流子效应．讨论了开态和关态应力．结果发现由于在漏端附近存在电荷注入,关态漏电流在较高的应力后会减小．但是低场应力后关态漏电流会增加,这是由于新生界面态的作用．结果还发现开态饱和电流和阈值电压在关态应力后变化很明显,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响．Idsat的退化可以用函数栅电流（Iｇ）乘以注入的栅氧化层电荷数（Qinj）的幂函数表达．最后给出了基于Idsat退化的寿命预测模型．     

Simulation of substrate hot-electron injection

Electron trapping in thin oxide and interface state generation has been investigated using a constant-current stressing technique. Assuming finite-temperature Fowler-Nordheim tunneling, semiempirical simulations of voltage versus stress time behavior were obtained for an MOS diode. A trapped charge model was used to simulate voltage versus stress-time behavior. The comparison between measurement and simulation results yields information about trapped charges in the oxide and at the oxide-substrate interface. The model can serve as the basis for improved understanding of the more complex phenomenon of channel hot-carrier injection in MOS transistors     

Modeling the anomalous threshold voltage behavior of submicrometerMOSFET's

A simple yet accurate semi-empirical analytical model for simulating the anomalous threshold voltage behavior in submicrometer MOSFETs is reported. The increase in the threshold voltage with decreasing channel length has been modeled by assuming a bias-independent, but channel-length-dependent, fixed charge at the source and drain ends. The new model requires two extra parameters in addition to the usual short-channel threshold voltage model parameters. These two parameters represent the magnitude of the fixed charge and the length over which the charge is spread at the source and drain ends. The model shows excellent agreement with the experimental threshold voltage data (within 2%) for submicrometer devices with varying oxide thickness, junction depth, and channel doping concentration     

基于FDSOI的TFET和MOSFET总剂量效应仿真

对基于全耗尽绝缘体上硅(FDSOI)的隧穿场效应晶体管(TFET)器件和金属氧化物半导体场效应晶体管(MOSFET)器件进行了总剂量(TID)效应仿真,基于两种器件不同的工作原理,研究了总剂量效应对两种器件造成的电学影响,分析了辐照前后TFET和MOSFET的能带结构、载流子密度等关键因素的变化。仿真结果表明:两种器件在受到较大辐射剂量时(1 Mrad (Si)),TFET受辐射引起的固定电荷影响较小,仍能保持较好的开关特性、稳定的阈值电压;而MOSFET则受固定电荷的影响较大,出现了背部导电沟道,其关态电流增加了几个数量级,开关特性发生了严重退化,阈值电压也严重地向负电压偏移。此外,TFET的开态电流会随着辐照剂量的增加而减小,这与MOSFET的表现恰好相反。因此TFET比MOSFET有更好的抗总剂量效应能力。     

A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation