0．13μm GGNMOS管的ESD特性研究

当ESD事件发生时,栅极接地NMOS晶体管是很容易被静电所击穿的。NMOS器件的ESD保护机理主要是利用该晶体管的骤回特性。文章对NMOS管的骤回特性进行了详细研究,利用特殊设计的GGNMOS管实现ESD保护器件。文章基于0．13μm硅化物CMOS工艺,设计并制作了各种具有不同版图参数和不同版图布局的栅极接地NMOS晶体管,通过TLP测试获得了实验结果,并对结果进行了。分析比较,详细讨论了栅极接地NMOS晶体管器件的版图参数和版图布局对其骤回特性的影响。通过这些试验结果,设计者可以预先估计GGNMOS在大ESD电流情况下的行为特性。     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

NMOS管Snapback特性ESD仿真模型研究

随着集成电路特征尺寸的不断缩小,ESD的问题始终困扰着芯片设计师们。文章提出了一种宏模型用于ESD的snapback仿真,它包含一个MOS管、一个NPN晶体管和一个衬底电阻,没有外部的电流源。简化的宏模型没有必要使用行为级的语言,如Verilog-A、VHDL-A。这使得仿真速度和收敛性得到提高。同时比较了三种先进的BJT模型:VBIC、Mextram、HICUM。模型参数可以通过模型参数提取软件(BSIMProPlus、ICCAP等)提取。     

三端双向负阻晶体管的二维数值模拟及分析

对双向负阻晶体管(BNRT)的三端特性进行了数值模拟，得到了器件S型负阻曲线。根据BNRT不同工作状态下的内部电势、电子浓度和空穴浓度分布，解释了其S型负阻特性的产生机理。模拟分析了负阻曲线随控制电压变化的情况。结果表明，随控制电压的增大，转折电压、转折电流和维持电压均增大。最后，对不同结构和工艺参数的三端BNRT进行了模拟，总结出器件结构和工艺参数对负阻特性的影响。     

High-current snapback characteristics of MOSFETs

The high-current snapback characteristics of MOSFETs with different channel lengths and widths, gate oxide thicknesses, and substrate dopings were studied to determine their effectiveness in electrostatic discharge stress protection. Filamentary conduction was not observed for currents up to 7 mA/μm of channel width for a pulsewidth of 500 ns. MOSFETs with shorter channel lengths require lower voltages to sustain the same current, independent of gate oxide thickness. Increasing the substrate doping does not necessarily reduce the high current voltage. These trends can be explained using a simple lateral n-p-n bipolar transistor snapback model     

Time-dependent snapback in thin-film SOI MOSFET's

During pulsed stressing of SOI MOSFETs for ESD characterization, the turn-on voltage of the parasitic bipolar transistor was observed to be a function of the stress pulse-width. This observation can be understood in terms of a capacitive charging model. The theory behind this time-dependent snapback is presented in this letter along with the experimental results. Comparisons with bulk-Si devices indicate that this phenomenon is specific to SOI and is a manifestation of the floating body effect     

埋栅型电力静电感应晶闸管的Ⅰ-Ⅴ特性反向转折机理

研究了静电感应晶闸管的反向转折特性.当工作在正向阻断态的阳极电压增大到某一临界值时,静电感应晶闸管的Ⅰ-Ⅴ曲线呈现出反向转折特性,甚至转向导通态.在综合考虑了工作机理、双注入效应、空间电荷效应、沟道中的电子-空穴等离子体和载流子寿命变化的基础上分析了静电感应晶闸管的反向转折特性.首次给出了反向转折机理的理论解释,并给出了估算转折电压和电流的数学表达式,在常用工艺参数范围内,计算结果和实验测量值基本一致.     

Pre-turn-on source bipolar injection in graded NMOSTs

The influence of the pre-turn-on source bipolar injection on graded NMOST breakdown characteristics is investigated. Double-implanted As-P (n⁺n^-) source-drain NMOS structures (DD NMOSTs) with different effective channel lengths, ranging from 1.15 to 9.15 μm, are measured. Using a simple, but accurate, semi-empirical model for the transistor operating in the breakdown region, it is shown that the DD NMOST snapback voltage is substantially decreased due to the enhanced pre-turn-on source electron emission current     

A latch phenomenon in buried N-body SOI NMOSFET's

The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V_GS is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current     

Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device

In this study, the effects of background doping concentration (BDC) of a high voltage operating extended drain N-type MOSFET (EDNMOS) device on electrostatic discharge (ESD) protection performances were evaluated. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.     

Laser interferometric method for ns-time scale thermal mapping of Smart Power ESD protection devices during ESD stress

A backside heterodyne interferometric technique is presented to study thermal effects in smart-power electrostatic discharge (ESD) protection devices during the ESD stress. The temperature increase in the device active area causes an increase in the silicon refractive index (thermo-optical effect) which is monitored by the time-resolved measurements of optical phase changes. Thermal dynamics and spatial temperature distribution in different types of npn transistor structures biased in the avalanche multiplication or snapback regime are studied with nanosecond time and micrometer spatial resolution. The activity and inactivity of the bipolar transistor action is indicated by the dominant signal arising from the emitter or base region, respectively. Hot spots have been found at the edges of the structures and attributed to the current crowding effect in the emitter.     

A model for the computer-aided noise analysis of broad-banded bipolar circuits

A model suitable for the prediction of equivalent input noise voltage, equivalent input noise current, and noise figure of narrow geometry integrated bipolar devices is presented. The bipolar model accounts for flicker phenomena and the low frequency current gain attenuation commonly observed at very low and at very high injection levels. Moreover, a first-order approximation to the dependence of intrinsic base resistance on transistor current level is analytically incorporated. Experimental results are offered and compared with analytical estimates gleaned from a computer program written to output pertinent noise performance data for frequencies below the beta-cutoff frequency of a transistor.     

一种有强健的续流开关的新型槽栅逆导IGBT

The phenomenon that the wide P-emitter region in the conventional reverse conducting insulated gate bipolar transistor （RC-IGBT） results in the non-uniform current distribution in the integrated freewheeling diode （FWD）, and then causes a parasitic thyristor to latch-up during its reverse-recovery process, which induces a hot spot in the local region of the device is revealed for the first time. Furthermore, a novel RC-IGBT based on double trench IGBT is proposed. It not only solves the snapback problem but also has uniform current distribution and high ruggedness during the reverse-recovery process.     

A Novel Body-tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current (I_DS-V_DS) curves, substrate resistance effect on the I_DS-V_DS curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.     

Two-dimensional carrier flow in a transistor structure under nonisothermal conditions

A two-dimensional mathematical model is developed to predict the internal behavior of power transistors operating under steady-state conditions. This model includes the internal self-heating effects in power transistors and is applicable to predict the transistor behavior under high-current and high-voltage operating conditions. The complete set of partial differential equations governing the bipolar semiconductor device behavior under nonisothermal conditions is solved by numerical techniques without assuming internal junctions and other conventional approximations. Input parameters for this model are the dimension of the device, doping profile, mobility expressions, generation-recombination model, and the boundary conditions for external contacts. Computer results of the analysis of a typical power transistor design are presented for specified operating conditions. The current density, electrostatic potential, carrier charge density, and temperature distribution plots within the transistor structure illustrate the combined effect of the electrothermal interaction, base conductivity modulation, current crowding, base pushout, space charge layer widening, and current spreading phenomena in power transistors.     

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

MOS cascode-mirror biasing circuit operating at any current levelwith minimal output saturation voltage

A cascode biasing circuit is proposed which fixes the source voltage of the cascode transistor equal to the saturation voltage of the mirror transistor. The mirror can operate at any current level from weak to strong inversion. The design is based on ratios, and is technology-independent. Since the circuit ensures the smallest possible output saturation voltage, it has potential applications in all fields of low-voltage micropower design     

光电双向负阻晶体管的数值模拟与实验研究

光电双向负阻晶体管(PBNRT)是一种新型S型光电负阻器件.本文对它的光电负阻特性进行了数值模拟和实验研究,给出了器件等效电路.PBNRT在光电混合工作模式下具有光控电流开关效应,可通过光照和控制电压两种控制方式改变器件的S型负阻特性.模拟和实验结果均表明:光照强度增大,维持电压基本保持不变,转折电压减小,负阻电压摆幅减小;而增大控制电压,维持电压和转折电压均增大,输出负阻特性曲线右移.上述特点使得PBNRT可望在光电开关、光控振荡和光电探测等方面有很好的应用前景.     

Analysis and compact modeling of a vertical grounded-base n-p-nbipolar transistor used as ESD protection in a smart power technology

A thorough analysis of the physical mechanisms involved in a vertical grounded-base n-p-n bipolar transistor (VGBNPN) under electrostatic discharge (ESD) stress is first carried out by using two-dimensional (2-D) device simulation, transmission line pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed     

逆导型沟槽FS IGBT的设计与实现

逆导型沟槽场终止绝缘栅双极型晶体管(RC Trench FS IGBT)是一种新型的功率半导体器件,具有成本低、体积小、可靠性高等优点.设计并实现了一款1200V逆导型沟槽FS IGBT.重点研究了逆导型绝缘栅门极晶体管(RC IGBT)特有的回扫现象,以及如何从结构设计上消除回扫现象,其次,对RC IGBT在不同的载流子寿命下,进行了开关特性、反向恢复特性的仿真.研究结果发现随着载流子寿命的降低,其开关时间、反向恢复特性都有一定程度的改善.依据器件的最优化设计进行了流片.测试结果验证了不同设计对电流回扫现象的影响,以及不同少子寿命下导通特性和反向恢复特性的变化规律,器件的性能得到优化.