基于国产平台的非易失功能模拟方法

为满足工程实践中对非易失内存的需求,在不对自主通用服务器主板进行重新设计修改的前提下,设计并实现一种基于软件模拟方法.通过修改操作系统内核以及驱动,将普通的易失性内存模拟为非易失内存,实现关机时数据保存以及开机时数据恢复功能.通过与NVDIMM-N非易失内存在执行时间以及读写性能方面进行对比,采用该模拟方法达到的效果整...     

MAC地址管控比对查询系统设计

电脑主板已作为网络设备的一种,在生产过程中有一重要的生产环节,那就是MAC地址的烧录及管控问题。建立一套系统实现电脑主板生产过程中对MAC地址的管控、比对、查询,以达到MAC地址的生产信息自动化管理,确保烧录到每片电脑主板中的MAC地址是全球唯一、有效的。     

计算机主板故障和维修探讨

为了更好的使用电脑,本人经过查询资料,上网搜索等途径,总结了一些有关电脑主板的知识。本文就计算机主板常出现的故障和其原因以及维修处理进行论述。     

Configuring of Algorithms in Mapping into Hardware

The growing need for high-performance embedded processors on the reconfigurable computing platform increases the pressure for developing design methods and tools. One important issue in mapping algorithms into hardware is the configuring of algorithms to fit the particular hardware structure, the available area and configuration, together with time parameters. This paper presents an overview of a new synthesis method—the Iso-plane method—on the polytope model of algorithm to increase the parallelism and facilitate the configurability in regular array design via algebraic transformations as associativity and commutativity. The paper presents a variety of new regular and scalable array solutions with improved performance and better layout including motherboards with daughter boards.     

便携式电路板自动测试系统的设计与实现

针对大型复杂装备电路母板故障诊断的测试需求,提出了一种基于USB总线接口的便携式自动测试系统;该系统采用Cy-press公司的EZ-USB FX2系列芯片CY7C68013实现USB2.0接口,同时EZ-USB单片机提供的I2C输出接口可以直接将来自主机的串型传输转换为I2C格式的数据进行输出,测试单元之间通过I2C总线互连,I2C收发器选择了I2C总线数据与8位并行数据转换的专用IC——PCA9501实现;该系统支持热插拔,可以实现高速快捷的故障定位;系统使用方便,可靠性高,已经在工程实际中使用。     

VMMB: Virtual Machine Memory Balancing for Unmodified Operating Systems

Virtualization technology has been widely adopted in Internet hosting centers and cloud-based computing services, since it reduces the total cost of ownership by sharing hardware resources among virtual machines (VMs). In a virtualized system, a virtual machine monitor (VMM) is responsible for allocating physical resources such as CPU and memory to individual VMs. Whereas CPU and I/O devices can be shared among VMs in a time sharing manner, main memory is not amendable to such multiplexing. Moreover, it is often the primary bottleneck in achieving higher degrees of consolidation. In this paper, we present VMMB (Virtual Machine Memory Balancer), a novel mechanism to dynamically monitor the memory demand and periodically re-balance the memory among the VMs. VMMB accurately measures the memory demand with low overhead and effectively allocates memory based on the memory demand and the QoS requirement of each VM. It is applicable even to guest OS whose source code is not available, since VMMB does not require modifying guest kernel. We implemented our mechanism on Linux and experimented on synthetic and realistic workloads. Our experiments show that VMMB can improve performance of VMs that suffers from insufficient memory allocation by up to 3.6 times with low performance overhead (below 1%) for monitoring memory demand.     

Employing transport layer multi-railing in cluster networks

Building clusters from commodity off-the-shelf parts is a well-established technique for building inexpensive medium- to large-size computing clusters. Many commodity mid-range motherboards come with multiple Gigabit Ethernet interfaces, and the low cost per port for Gigabit Ethernet makes switches inexpensive as well. Our objective in this work is to take advantage of multiple inexpensive Gigabit network cards and Ethernet switches to enhance the communication and reliability performance of a cluster. Unlike previous approaches that take advantage of multiple network connections for multi-railing, we consider CMT (Concurrent Multipath Transfer) that extends SCTP (Stream Control Transmission Protocol), a transport protocol developed by the IETF, to make use of the multiple paths that exist between two hosts. In this work, we explore the applicability of CMT in the transport layer of the network stack to high-performance computing environments. We develop SCTP-based MPI (Message Passing Interface) middleware for MPICH2 and Open MPI, and evaluate the reliability and communication performance of the system. Using Open MPI with support for message striping over multiple paths at the middleware level, we compare the differences in supporting multi-railing in the middleware versus at the transport layer.     

A memory interference model for regularly patterned multiple streamvector accesses

Most existing analytical models for memory interference generally assume random bank selection for each memory access. In vector computers, however, memory accesses are typically regularly patterned with a number of data items being accessed concurrently from different banks. Very little is known about the queueing behavior of memory interferences in multiple stream vector accesses. This paper presents an analytical model for memory interferences due to vector accesses in multiple vector processor systems. The model captures the effects of both bank conflicts among elements within one vector access stream and conflicts among multiple vector access streams on system performance. The model is based on a closed queueing network assuming an ideal interconnection network. An approximation technique is proposed to solve the memory queueing system that serves customers in a complicated way (non-FIFO). We also carry out extensive simulation experiments to study memory interference and validate our analytical model. Simulation results and analytical results are in a very good agreement, indicating that the model is very accurate. We further validate our analysis by comparing the numerical results obtained from our analytical model with those measurement results that were published by other researchers. Based on our analytical model and simulations, we carry out performance evaluation of the multiple vector processor systems. Our numerical results show that memory access conflicts pose a severe limitation on the number of useful processors in the system, implying that memory system design is essential to high-performance computing     

Evolutionary Model of Optimization of Modular Associative Memory for Dataflow Machines Based on Genetic Algorithm

An evolutionary model of modular associative memory for machines with dataflow architecture is suggested. A problem of determination of optimal allocation of a dataflow in a computational system with modular associative memory is formulated. The model suggested is based on graph representation of the dataflow. The allocation of the dataflow among modules is realized by means of a hash function. A method for searching for optimal hashing with the use of a genetic algorithm is suggested. The convergence of the genetic algorithm is studied. Estimates of optimal allocation among modules of associative memory for various computational problems are obtained.     

数值计算程序的存储复杂性分析

由于越来越多的技术用于缩小处理器与存储器之间的日益加大的速度差距,计算机的存储系统变得日趋复杂．现在,任何一个程序设计者,尤其是数值计算程序的设计者,若不考虑其所用计算平台存储系统的特点是很难获取高性能的．因此公用传统的算法评价方法,从时间复杂性和空间复杂性着手来解释一个算法的不同实现在同一计算平台上很大的性能差异,显然是不够的．计算平台存储系统的特点必须在分析算法的复杂性时加以考虑．孙家昶１９９     

Relationships between memory models

There have been many proposals of shared memory systems, each one providing different types of memory coherence for interprocess communication. However, they have usually been defined using different formalisms. This makes it difficult to compare among them the different proposals put forward. In this paper we present a formal framework for specifying memory models with different coherency properties. We specify most of the known shared memory models using our framework, showing some of the relationships that hold among them.     

云计算平台中多虚拟机内存协同优化策略研究

虚拟化技术为云计算基础设施资源的动态部署、安全隔离提供了重要保证.从过度占用内存的虚拟机中回收内存,提供给内存紧缺的虚拟机使用,优化多虚拟机间的内存分布是内存虚拟化中的挑战性问题.文中引入了自发调节和全局调节协作的多虚拟机内存管理架构.通过定义内存资源充裕状态和内存资源紧缺状态,提出了自发调节和全局调节之间协作的算法....     

基于模式关联的一对多联想记忆方法

在现有的多模块一对多联想记忆模型中,由于所处理的记忆模式集合本身的特点以及记忆模式之间的关联被忽视,使得构造出来的模型结构复杂,难以实际应用.针对这一不足,提出一种基于模式关联的实现方法.以该方法构造出的多模块一对多联想记忆模型结构简单,易于硬件实现,使得多模块一对多联想记忆模型具有了实际应用的可能.     

Visual capability to receive character information. Part I: How many characters can we recognize at a glance?

A study was made on the capability to receive character information and the factors restricting it. The study showed that the capability indicated by the memory span was limited by the average number of characters for words that are made up of individual characters, and calculated in terms of information quantity, there was no difference among the individual characters. The differences in memory span, depending on the size of the pattern presented, was negligible. The difference in the way characters were arranged produced the difference in memory span saturation. This phenomenon is explained by the nature of the lateral interference effect working among the adjacent characters.     

在操作系统中实现处理机进程和存储进程的分离

通过为进程分配和回收处理机资源和存储器资源，传统操作系统实施对处理机和存储器的管理和控制，在多处理机操作系统中，当处理机和存储器之间的互连方式比较复杂时，仅仅构造唯一一种进程抽象，不能很好地实施对处理机资源和存储器资源的管理，基于以上思想，在操作系统中应该构造两类进程抽象；处理机进程和存储进程，并实现处理机进程和存储进程的分离，首先分析了构造两类进程抽象（处理机进程和存储进程）并实现二者分离的原因，根据分析提出了实现处理进程和存储进程分离的方法。     

Tetris: A Heuristic Static Memory Management Framework for Uniform Memory Multicore Neural Network Accelerators

Uniform memory multicore neural network accelerators (UNNAs) furnish huge computing power to emerging neural network applications. Meanwhile, with neural network architectures going deeper and wider, the limited memory capacity has become a constraint to deploy models on UNNA platforms. Therefore how to efficiently manage memory space and how to reduce workload footprints are urgently significant. In this paper, we propose Tetris: a heuristic static memory management framework for UNNA platforms. Tetris reconstructs execution flows and synchronization relationships among cores to analyze each tensor’s liveness interval. Then the memory management problem is converted to a sequence permutation problem. Tetris uses a genetic algorithm to explore the permutation space to optimize the memory management strategy and reduce memory footprints. We evaluate several typical neural networks and the experimental results demonstrate that Tetris outperforms the state-of-the-art memory allocation methods, and achieves an average memory reduction ratio of 91.9% and 87.9% for a quad-core and a 16-core Cambricon-X platform, respectively.     

一种面向GPGPU的行为感知的存储调度策略

随着通用图形处理器在高性能计算领域的广泛应用,新的并行执行模式被提出。在新模式下,当前的存储调度策略未能使存储器的吞吐率达到最大。分析了图形处理器上多程序并行执行模式下应用程序访存行为特征及其性能损失不公平的原因,提出了一种基于访存行为感知的存储调度策略,利用不同程序类型的优势进行优先级调度。实验表明,该方法能够明显改善不同类型程序间性能损失不均衡的问题,相比基准结构对所有测试程序的存储系统吞吐率和公平性分别有平均9.7%和15.0%的提升。     

一种基于PCI总线的反射内存卡设计

设计了一款基于PCI总线的反射内存卡。在FPGA中设计了数据存取控制逻辑、SDRAM控制逻辑,避免了内存冲突,实现内存共享;利用FIFO进行数据缓冲,提高了数据传输速率;设计了数据包格式,以支持组建反射内存网络;采用光纤接口传输数据,串行传输速率达1.0625 Gb/s。开发了基于Windows的设备驱动程序,提供了Windows API函数。仿真实验表明,该卡能够完成不同节点间的实时传输。     

Super－Object模型：在分布存储器多计算机上实现共享存储器程序设计模式

Ｓｕｐｅｒ－Ｏｂｊｅｃｔ模型提出了一种新的方法，在分布存储器多计算机上实现语言级虚拟共享存储器以支持共享存储器通信模式．Ｓｕｐｅｒ－Ｏｂｊｅｃｔ模型引入新的概念ｓｕｐｅｒ－ｏｂｊｅｃｔ，不同于其它模型，基于ｓｕｐｅｒ－ｏｂｊｅｃｔ，它提出了新的共享数据定位方法，全局地址标识（ｎａｍｅ，ｏｆｆ－ｓｅｔ）．Ｓｕｐｅｒ－Ｏｂｊｅｃｔ模型与Ｆｏｒｔｒａｎ７７结合，我们实现了一个运行时间系统和库调用，支持程序员使用Ｆｏｒｔｒａｎ语言编写并行程序，最后介绍了系统的实现和取得的性能．     

Delay tolerant lazy release consistency for distributed shared memory in opportunistic networks

Opportunistic networks (ONs) allow mobile wireless devices to interact with one another through a series of opportunistic contacts. While ONs exploit mobility of devices to route messages and distribute information, the intermittent connections among devices make many traditional computer collaboration paradigms, such as distributed shared memory (DSM), very difficult to realize. DSM systems, developed for traditional networks, rely on relatively stable, consistent connections among participating nodes to function properly.We propose a novel delay tolerant lazy release consistency (DTLRC) mechanism for implementing distributed shared memory in opportunistic networks. DTLRC permits mobile devices to remain independently productive while separated, and provides a mechanism for nodes to regain coherence of shared memory if and when they meet again. DTLRC allows applications to utilize the most coherent data available, even in the challenged environments typical to opportunistic networks. Simulations demonstrate that DTLRC is a viable concept for enhancing cooperation among mobile wireless devices in opportunistic networking environment.