Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.     

Flow time measurements for underfills in flip-chip packaging

Flow time is a key material property for underfill materials in flip-chip applications. In this paper, we will discuss how to use flow time testing for underfill flow evaluation and material screening. The flow time of several underfills was measured at elevated temperatures using test pieces made from glass microscope slides. The material properties impacting underfill flow, such as viscosity, contact angle, and surface tension, were also experimentally measured and used to calculate estimated flow times using the Washburn equation. Empirical and calculated flow times were compared. The effects of channel width and flow distance on flow time were also studied. Additionally, the effect of a tilted stage on flow time, epoxy tongue, and void formation was evaluated.     

微电子封装技术的发展与展望

微电子技术的发展,推动着微电子封装技术的不断发展、封装形式的不断出新。介绍了微电子封装的基本功能与层次,微电子坟技术发展的三个阶段,并综述了微电子封装技术的历史、现状、发展及展望。     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

数字显示电路的设计与多芯片组件封装实现

由于MCM自身的特点，物理设计已成其瓶颈问题。本文在已有方案的基础上，设计实现了一个数字显示电路，并计算了各单元电路的相关参数，最后对电路进行多芯片组件(MCM)封装。仿真结果表明，该电路的最大电容量和响应时间等参数均能满足电路设计的要求。     

Recent advances in device processing and packaging of high-power pulsed GaAs double-drift IMPATT's at X-band

High-power multimesa GaAs hybrid double-drift IMPATT's have been developed for pulsed operation at X-band. The diodes are fabricated from GaAs material grown by a novel "infinite" solution liquid phase epitaxial process. The use of specialized rapid thermal processing and packaging techniques has enabled the fabrication of high-power IMPATT oscillators that have delivered peak output powers of over 40 W with 20-percent efficiency under pulsed RF operation at X-band frequencies. The diodes are constructed with an integral heat sink and bounded with a Au-Sn eutectic solder in a microwave package.     

Recent advances in metasurface hologram technologies (Invited paper)

Since Leith and Upatnieks demonstrated the first optical hologram in 1964, hologram technology has attracted a great deal of interest in a wide range of optical fields owing to its potential use in future optical applications such as holographic imaging and optical data storage. Although there have been considerable efforts to develop holographic technologies using conventional optics, critical issues still hinder future development. Recently, metasurfaces composed of artificially fabricated subwavelength structures have been considered as novel holographic devices that show an unprecedented ability to control electromagnetic waves. In this review, we outline the recent progress in metasurface holography. A general introduction to several types of metasurface holography categorized based on their physics and application is provided. Then, our personal perspective on the future of this field is discussed.     

Current capabilities/needs and future possibilities of multichipmodules (MCM's)

Summary form only given. The state of the art was discussed in terms of costs, densities, speeds, sizes, yields, rework, testing methodologies, and thermal capabilities for the principle production interconnects. Comparisons were made for each of the newer MCM (multichip module) technologies for which data are available. Observations about costs, reworkability, assembly methods, yields, and testing were made to indicate the author's views on where and how costs for MCMs can be driven down to become competitive with existing interconnect systems     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

微电子金属封装温度场仿真系统的研究

基于ANSYS平台，利用VC语言开发了一个专门针对微电子金属封装温度场的仿真系统。可以对不同情况下的微电子金属封装进行温度场仿真，并查看仿真结果。用VC语言编程，用户只需输入必要的前处理参数，就可以得出ANSYS的封装仿真结果，从而使不了解ANSYS的用户也可利用其强大的功能进行计算和分析。     

High-yield flip-chip bonding and packaging of low-threshold VCSEL arrays on sapphire substrates

Oxide-confined top-emitting 850 nm and bottom-emitting 980 nm vertical-cavity surface-emitting laser (VCSEL) 8/spl times/8 arrays were designed and fabricated for applications of optical interconnects. The arrays were flip-chip bonded onto sapphire substrates that contain complimentary metal-oxide-semiconductor (CMOS) driver and fan-out circuitries. The off-sited bonding contacts and minimized bonding force produced very high yield of the hybridization process without causing damage to the VCSEL mesas. The hybridized devices were further mounted either on printed circuit board (PCB) or in 68-pin pin-grid-array (PGA) packages. The transparent sapphire substrate allowed optical outputs from the top-emitting VCSEL arrays to transmit directly through without additional substrate removal procedure. Lasing thresholds below 250 /spl mu/A for 850 nm VCSELs and 800 /spl mu/A for 980 nm VCSEL were found at room temperature. The oxide confinement apertures of VCSELs were measured to be around 6 /spl mu/m in diameter. High-speed data transmission demonstrated a bandwidth of up to 1 Gbits/s per channel for these hybridized VCSEL transmitters.     

Residual stresses in microelectronics induced by thermoset packaging materials during cure

This paper presents a constitutive model for predicting the stresses in thermosetting resins during cure. An overview is given of the experimental techniques used for determining the parameters in this model. The model is validated by comparing its predictions to additional measurements, which have not been used for the actual parameter estimation. This validation showed that the model is capable of giving fair predictions of the measured stresses. The model is implemented in a commercially available finite element package and its use is demonstrated by applying it to the study of a flip-chip underfilling process.     

Numerical investigation and experimental validation of residual stresses building up in microelectronics packaging

This paper comprises the numerical approach and the experimental validation technique developed to obtain the residual stresses building up during encapsulation process of integrated circuits. Residual stresses can be divided into cure and cooling induced parts. The curing originated stress had been mostly neglected in the literature and a special attention had always been given to detection of the thermal induced stress. In this study, both of the residual stresses, evolving during packaging, were investigated independently. The material behavior of the epoxy molding compound, EMC, was determined by the series of characterization experiments. The volumetric behavior of the EMC was investigated using PVT analysis, in which the total cure shrinkage of an initially uncured sample and the coefficient of thermal expansion of the same sample after full conversion were determined. The cure kinetics was studied using differential scanning calorimetry, DSC. The dynamic mechanical behavior was examined by dynamic mechanical analysis, DMA, at a fixed frequency. Besides, the time dependent behavior of the EMC was also determined by implementing the time–temperature superposition, TTS, test set-up in DMA. The shift factor was modeled using the combination of the WLF equation and the polynomial of second degree. The constitutive equations were developed based on the applied boundary conditions and the epoxy compound's mechanical behavior in the respective stage. A two dimensional numerical model was constructed using a commercially available finite element software package. For the experimental verification of the numerically obtained residual stresses a flexible board with the stress measuring chip was encapsulated. The real-time stress data were measured during the encapsulation. Using this technique, the in-plane stresses and the temperature changes during the die encapsulation were measured successfully. Furthermore, the measured stress data was compared with the predicted numerical results of the cure and the thermal stages, independently.     

Formulation and characterization of anisotropic conductive adhesive paste for microelectronics packaging applications

There has been a steadily increasing interest in using electrically conductive adhesives as interconnecting materials in electronics manufacturing. In this paper, several anisotropic conductive adhesive (ACA) pastes were formulated, which consist of diglycidyl ether of bisphenol F or diglycidyl ether of bisphenol A as polymer matrix, imidazoles as curing agents, and different sizes of silver (Ag) powders or gold (Au)-coated polymer spheres as conductive particles. The effects of ACA resin and different curing agents, as well as different conductive particles, on flexible substrate of the flip-chip joint were studied. The results show that the size and type of different conductive particles have very limited influence on an ACA flip-chip joint. The ACA resin as well as the curing agent can affect the reliability of the joint. The same results can be applied for the failure analysis of ACA flip-chip technology.     

Self-aligned flip-chip packaging of tilted semiconductor opticalamplifier arrays on Si motherboard

An optical self-aligned flip-chip packaging technique for tilted semiconductor optical amplifier arrays is reported. It uses a Si motherboard with V-grooves for self-alignment between the tilted SOA array and angle polished fibre arrays. Fibre-to-fibre gain of 14±1 dB and ripple ±0.1 dB without antireflection coating on the fibres have been achieved     

Chemothermal modeling and finite-element analysis for microwave cure process of underfill in flip-chip packaging

The reaction kinetics of microwave cure process of underfill materials in flip-chip packaging was investigated with nonisothermal kinetic method and compared with that of the thermal cure. Three-dimensional (3-D) nonlinear cure kinetic and transient heat transfer coupled model was solved by finite-element method (FEM) to simulate the microwave cure process. The accuracy of the program was verified using a simple heat conduction case by commercial FEM software. Temperature and conversion inside underfill during microwave cure process were evaluated by solving the nonlinear anisotropic heat conduction equation including internal heat generation produced by exothermic chemical reactions. Numerical results show that the iteration calculations are very sensitive to small changes in time step sizes. It was also found that variable frequency microwave can process underfill materials with uniform conversion under different curing temperatures.