A loop phase-locked 74 GHz impatt oscillator usable for precise spectroscopy to the 500 GHz region

To examine possible application to spectroscopy and laser frequency measurement, a 74 GHz impatt oscillator was phase-locked to a quartz-crystal oscillator harmonic using a loop employing a digital phase-frequency detector. The maximum frequency multiplication permissible without catastrophic spectral broadening was estimated from the locked-phase spectral-density curve to be about 7 times, to 500 GHz, a factor 3 less than for a good-quality well locked reflex klystron, because of greater phase noise remaining outside the loop bandwidth. The use of wideband loops already existing for solid-state oscillators could suppress this disadvantage.     

A power-efficient wide-range phase-locked loop

This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-μm CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations     

A 2-V amplitude-linear phase-locked loop

An amplitude-linear phase-locked loop which consumes less than 1 mW from a 2-V supply when operating at 100 kHz has been implemented in conventional 4-/spl mu/m CMOS. Obtaining reliable MOS analog operation at low voltages constrains the circuit approaches available and forces large device geometries. Sample-data techniques are applied to realize a low-voltage CMOS equivalent to the bipolar multiplier, and a voltage-controlled oscillator control buffer is used to define a linear frequency characteristic. The measured performance demonstrates suitability for portable tone-decoding and FM demodulation applications.     

A low-noise phase-locked loop design by loop bandwidth optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively     

1.2V 6GHz 1.19mW 32/33前置分频器的设计

基于4/5双模SCL分频结构设计了一个高速、低压、低功耗的32/33双模前置分频器。该设计基于TSMC90nm1P9M CMOS工艺,利用Mentor Graphics Eldo工具仿真,结果表明该分频器最高工作频率达6GHz,在电源电压1.2V,输入6GHz情况下,功耗仅1.19mW。     

A 6-GHz integrated phase-locked loop using AlGaAs/GaAsheterojunction bipolar transistors

A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking range was measured to be greater than 750 MHz at zero steady-state phase error. The nonaided acquisition range is approximately 300 MHz. This circuit is the first monolithic HBT PLL and is the fastest yet reported using a digital output VCO. The minimum emitter area was 3 μm×10 μm with f_t=22 GHz and f_max=30 GHz for a bias current of 2 mA. The speed of the PLL can be doubled by using 1-μm×10-μm emitters in next-generation circuits. The chip occupies a die area of 2-mm×3-mm and dissipates 800 mW with a supply voltage of -8 V     

A 1320 nm experimental optical phase-locked loop

An experimental balanced optical second-order phase-locked loop constructed using 1320 nm diode laser pumped miniature Nd:YAG lasers is discussed. The loop is stable and has a phase error of less than 1.8° when the received signal power is -65 dBm or more. The phase error appears to be dominated by the lasers' frequency noise as long as the signal power is more than -60 dBm     

A high lock-in speed digital phase-locked loop

A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model. The advantages of the proposed DPLL are: high lock-in speed, no steady-state frequency tracking error even for period ramp input signals; and ease of integration into a single chip. The use of the DPLL to realize the pitch synchronous analysis of voiced speech is reported     

A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

A 2-GHz 1.6-mW phase-locked loop

This paper describes the design of a 2 GHz 1.6 mW phase-locked loop (PLL) fabricated in an 18 GHz 0.6 μm BiCMOS technology. Employing cross-coupled delay elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipation. An experimental prototype exhibits an r.m.s. jitter of 2.8 ps, a tracking range of 100 MHz, and a capture range of 70 MHz while operating from a 3 V supply. The phase noise in the locked condition is -115 dBc/Hz at 400 kHz offset     

18GHz 600mW GaAs MESFET

本文介绍了DX621型GaAsMESFET的设计与制作。该器件成功地采用了密集型源区正面通孔电镀热沉结构,同时采用了N~+N~-N特殊杂质浓度分布的汽相GaAs外延材料。该器件在18GHz下,1dB压缩输出功率大于600mW,1dB压缩功率增益为7dB,漏极效率大于30％。     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

一种新型2.4 GHz SiGe BiCMOS低噪声放大器

基于窄带低噪声放大器理论,设计了一种2.4 GHz,具有低功耗、低噪声和良好匹配性等优点的新型BiFET结构SiGe BiCMOS低噪声放大器。采用TSMC 0.35μm SiGe BiCMOS工艺库,利用SpectreRF软件的仿真结果显示,该电路具有2.27 dB低噪声系数,11.5 dB正向增益;2 V工作电压下,其功耗仅为6.1 mW。研究结果表明,该低噪声放大器在射频蓝牙系统中具有一定的应用前景。     

A low-noise fast-lock phase-locked loop with adaptive bandwidthcontrol

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range     

A monolithic phase-locked loop with post detection processor

Describes the design and fabrication of a high-frequency (50-MHz) phase-locked loop with a post detection processor which allows the detection of FSK signals with few external components. The circuit operates with a single 5-V supply and has TTL compatible inputs and outputs.     

Very wide range phase-locked loop

A phase-locked loop is described that will capture and lock to any input frequency in the range 1 Hz to 1 MHz without any adjustment. A DC signal proportional to the logarithm of the input frequency is available.     

A multidimensional phase-locked loop for blind multiuser detection

This paper concerns the problem of blind multiuser detection, a special case of the blind source separation problem in which the source signals have finite alphabets. Specifically, we address the problem of identifying and resolving the n/spl times/n unitary matrix ambiguity U that results from whitening the receiver observations, where n is the number of sources. We propose the multidimensional phase-locked loop (MPLL) as a generalization of a scalar decision-directed PLL to vector-valued signals. The MPLL adapts an estimate of U according to the recursion U/spl circ//sub k+1/=U/spl circ//sub k/R/sub k/, where R/sub k/ is an n-dimensional Householder-like rotation depending on only the kth receiver observation. The O(n/sup 2/) complexity of an efficient implementation of the algorithm is extremely low. Nevertheless, simulation results demonstrate good convergence properties and superior steady-state performance when compared with prior techniques. The algorithm is also able to accommodate large alphabets and shaped alphabets.     

5 GHz, 12 mW NMOS frequency divider

Reports on the development of an NMOS 2:1 frequency divider circuit that operates to over 5 GHz. It is powered from a 2.5 V supply and dissipates only 0.012 W. These results indicate that the use of silicon MOS technology may be extended to very-high-speed low-power applications