Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling, subthreshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict and reduce subthreshold leakage power of such systems. In the first part of this paper, we present a subthreshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18-/spl mu/m CMOS confirm that the mean error of the model is 4%. In the second part of this paper, we present the use of stacked devices to reduce system subthreshold leakage power without reducing system performance. A model to predict the scaling nature of this stack effect and verification of the model through statistical device measurements in 0.18-/spl mu/m and 0.13-/spl mu/m are presented. Measurements also demonstrate reduction in threshold voltage variation for stacked devices compared to nonstack devices. Comparison of the stack effect to the use of high threshold voltage or longer channel length devices for subthreshold leakage reduction is also discussed.     

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V _th, channel length L and gate oxide thickness t _ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.     

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling     

Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

Power switch transistors are very effective in cutting the leakage currents of digital circuits in a deep-freeze mode, by de-supplying unused blocks. Among existing power switch transistors, Super Cut-off CMOS (SCCMOS) is the most suited to a low supply voltage environment since it uses a low threshold voltage transistor. This power switch type achieves good leakage reduction results, provided that an optimal voltage is applied on its gate in order to maximize the leakage gain. This optimal voltage value, depending on the operating conditions (process, voltage, temperature), cannot be determined at the design level. A polarization circuit, that automatically finds the optimal bias voltage whatever the environment conditions, was therefore designed and fabricated. This circuit, made in Bulk 65 nm technology, achieves more than two decades leakage current reduction at the power switch level, for a power dissipation overhead of 45 nW at ambient temperature. A very simple scheme is also presented to alleviate the voltage stress applied on the dielectric in case of an ageing of the latter, increasing its time-to-breakdown by several orders of magnitude.     

Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8?V, 75°C demonstrate power reduction by 59.4% in case of 1?bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1?bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45?V applied in active mode improves the maximum operating frequency by 16% in case of 1?bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.     

LECTOR: a technique for leakage reduction in CMOS circuits

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCTs is always "near its cutoff voltage" for any input combination. This increases the resistance of the path from V/sub dd/ to ground, leading to significant decrease in leakage currents. The gate-level netlist of the given circuit is first converted into a static CMOS complex gate implementation and then LCTs are introduced to obtain a leakage-controlled circuit. The significant feature of LECTOR is that it works effectively in both active and idle states of the circuit, resulting in better leakage reduction compared to other techniques. Further, the proposed technique overcomes the limitations posed by other existing methods for leakage reduction. Experimental results indicate an average leakage reduction of 79.4% for MCNC'91 benchmark circuits.     

基于施密特触发的高鲁棒性亚阈值标准单元

亚阈值电路是低功耗重要发展方向之一.随着电源电压降低,晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响,已经成为制约亚阈值芯片的瓶颈.该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案.该方案首先利用ST的迟滞效应与反馈机制,在电路堆叠结点处添加施密特反馈管以优化逻辑门、减...     

A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V _DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.     

一种基于UC3844的多路输出电源设计

阐述了一种基于UC3844 PWM(脉宽调制)控制器的新型多路输出反激式开关电源电路的设计。给出了变压器、漏感消除电路、启动电路以及电压电流反馈电路的设计过程。实验结果表明,该电源性能优良,具有稳压效果好、纹波小、负载调整率高等优点。作为电机控制的电源模块,具有很高的应用价值。     

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies

Parametric yield loss has become a serious concern in nanometer technologies. In this paper, we propose a methodology to estimate and optimize the parametric yield of a design in the presence of process variations. We discuss the impact of leakage on parametric yield given that leakage causes the parametric yield window to shrink by imposing a two-sided constraint in conjunction with performance targets on the yield window. We present a mathematical framework for yield estimation under process variation for a given power and frequency constraints. The model is validated against Monte Carlo SPICE simulations in a 90-nm CMOS process and is shown to have a typical error of less than 5%. We then demonstrate the importance of optimal supply and threshold voltage selection for yield maximization. Our results show that parametric yield is highly sensitive to supply voltage with only a 5% change in the supply voltage potentially leading to nearly 15% yield degradation. We also investigate the sensitivity of parametric yield to required frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.     

A Low Voltage and Power LC VCO Implemented With Dynamic Threshold Voltage MOSFETS

A 1.1-GHz voltage control oscillator (VCO) using a standard 0.18-mum CMOS 1P6M process is fabricated. The VCO was designed with dynamic threshold voltage metal-oxide-semiconductor field-effect transistors and extremely-low-voltage and low power operation is achieved using on-chip transformers in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. This VCO prototype is designed for a 0.34-V supply voltage while the output phase noise is -121.2dBc/Hz at 1-MHz offset frequency at the carrier frequency of 1.14GHz, the figure of merit is -192.0dB. The total power consumption is 103.7muW with the 0.34-V supply voltage. Tuning range is from 1.06 to 1.14GHz about 80MHz while the control voltage was tuned from 0 to 1.8V. The die area is 0.625times0.79mm²     

Performance and reliability design issues for deep-submicrometerMOSFETs

Device design constraints, such as threshold voltage variation due to short-channel and drain-induced-barrier-lowering effects, off-state leakage current due to punchthrough and gate-induced drain leakage, hot-carrier effects such as hot-electron degradation and avalanche breakdown, and time-dependent dielectric breakdown, are examined. The current-driving capability, ring-oscillator switching speed, and small-signal voltage gain are examined. The impact that each of these factors has on the allowable choice of MOSFET channel length, oxide thickness, and power supply voltage is examined. Based on experimental results, a set of design curves, using a set of typical performance and reliability criteria, is presented for deep-submicrometer nonlightly doped drain (non-LDD) n-channel devices. From these curves, the relative importance of each particular performance/reliability mechanism for a given technology and design criteria can be determined. Because the performance and reliability issues addressed are also relevant to other MOSFET technologies, the design guidelines can also be extended to other technologies, including p-channel and LDD devices     

Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control

This paper presents the design and measured performance of a 1.8-GHz power amplifier featuring load mismatch protection and soft-slope power control. Load-mismatch-induced breakdown can be avoided by attenuating the RF power to the final stage during overvoltage conditions. This was accomplished by means of a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. The issue of output power control has been addressed as well. To this end, a temperature-compensated bias network is proposed, which allows a moderate power control slope (dB/V) to be achieved by varying the circuit quiescent current according to an exponential law. The nonlinear power amplifier was fabricated using a low-cost silicon bipolar process with a 6.4-V breakdown voltage. It delivers a 33.5-dBm saturated output power with 46% maximum power-added efficiency and 36-dB gain at a nominal 3.5-V supply voltage. The device is able to tolerate a 10:1 load standing-wave ratio up to a 5.1-V supply voltage. Power control slope is lower than 80 dB/V between -15 dBm and the saturated output power level.     

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power–delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power–delay performance of these two topologies is proposed.      

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.     

Enhancement-mode power heterojunction FET utilizingAl0.5Ga0.5As barrier layer with negligibleoperation gate current for digital cellular phones

We have developed a novel enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET (HJFET) with a 5 nm thick Al_0.5Ga_0.5As barrier layer inserted between an In _0.2Ga_0.8As channel layer and an upper Al_0.2 Ga_0.8As electron supply layer. The Al_0.5Ga _0.5As barrier layer reduces gate current under high forward gate bias voltage, resulting in a high forward gate turn-on voltage (V _F) of 0.87 V, which is 170 mV higher than that of an HJFET without the barrier layer. Suppression of gate current assisted by a parallel conduction path in the upper electron supply layer was found to be also important for achieving the high V_F. The developed device exhibited a high maximum drain current of 300 mA/mm with a threshold voltage of 0.17 V. A 950 MHz PDC power performance was evaluated under single 3.5 V operation. An HJFET with a 0.5 μm long gate exhibited 0.92 W output power and 63.6% power-added efficiency with 0.08 mA gate current (I_g) at -48 dBc adjacent channel leakage power at 50 kHz off-center frequency. This I_g is one-thirteenth to that of the HJFET without the barrier layer. These results indicate that the developed enhancement-mode HJFET is suitable for single low voltage operation power applications     

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic