Low-power C-R hybrid D/A conversion network for SAR A/D converter

An energy-efficient D/A conversion structure combined with a splited unit-capacitor array and an intermittent-sleeping resistor string is presented for low power SAR A/D converter. The energy dissipation and the matching requirement of the D/A conversion network are researched based on Matlab modeling. And its superiority and applicability are proven by the realization of an 8-bit 200kS/s 25.6 μW 65 nm CMOS SAR A/D converter with this proposed D/A structure.     

A/D and D/A conversion for telecommunication

Emerging telecom systems such as ADSL and VDSL demand state-of-the-art high speed and high resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DBCs). Moreover, cost and power consumption issues require the use of specific A/D and D/A architectures to achieve the wanted resolution at the required speed at minimum power. In the first part of this article we present an overview of the various ADC and DAC architectures used in Alcatel Telecom systems over the past 15 years, with an emphasis placed on the evolution of ADCs and DACs for today's asymmetrical-digital-subscriber-loop (ADSL) applications. We then discuss design considerations for high-speed and high resolution ADCs for future very-high-data-rate digital subscriber-line (VDSL) technology     

On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs

It has recently shown how a constant dc offset between two low-quality test signals can be used to test the integral nonlinearity (INL) of A/D converters (ADCs) without an accurate test stimulus, and how the same method can be used to test the INL of D/A converters (DACs) as well. We propose here an on-chip offset generator for producing the constant offset and analyse its limitations. Experimental tests on the 122 × 22 μm² offset generator fabricated in 130 nm CMOS process show that it can be used to test the INL of 12-b DACs and ADCs. The generator is rail-to-rail capable so that almost the whole input/output range of converters can be tested. Moreover, if the proposed offset generator is used in a ratiometric test setup as proposed here as well, the influence of a reference voltage drift on measurement accuracy is cancelled out. Because of its small size, simple design, rail-to-rail capability and immunity to reference voltage changes, the proposed offset generator is well suited for built-in self-test usage.     

Modeling modulators for A/D signal conversion

The performance of an SDM is reported to decline by various factors produced during the design and fabrication process. Namely, the nonideal factors are: the limit of the operational amplifier (op-amp) output swing, the finite DC gain of the op-amp, op-amp slew rate, the integrator gain error by mismatching of the capacitor and nonideality of the internal multibit quantizer. In this article we report not only modeling results of the ideal second-order SDM with a multibit quantizer, but also evaluate its performance according to bit number and OSR. In addition, we determine the maximum error limit of the SDM after investigating the influence of the nonideal factors on the performance of the SDM     

Efficient real-time interpolation for D/A conversion

Four interpolation schemes using small sample sets are considered for real-time D/A conversion applications. Evaluation, for sampling rates near the Nyquist limit, is based on a mean-square-error criterion. Hardware suitability is considered with respect to the number of operations per interpolation and degree of parallelism.     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

Monotonic dual-ladder A/D conversion

The use of a monotonic ladder network in a two-stage n-bit flash A/D convertor is examined. The technique is verified by a 6-bit discrete ADC. High-speed and monotonic operation are theoretically impossible in a two-step flash converter with this technique. This method allows for a reduction in the required circuit die size, while maintaining the conversion speed of a flash A/D converter.     

D/A conversion interface design for DMT-ADSL applications

For high-speed internet access, high-performance analog front-ends are needed, and data converters are one of the crucial building blocks in these bent-ends. In this article we will report on the modeling and design of a D/A conversion interface for a DMT (discrete multi tone)-based ADSL system that could be integrated into a complete CMOS analog front-end. We will discuss the DMT transmit spectrum and its impacts on data converters, we will focus on modeling and simulating of the whole D/A interface, and we will describe a test chip implemented in a 0.6 μm CMOS process     

Binary weighted D/A converters with mismatch-shaping

A D/A convertor suited to multibit sigma-delta modulators is described. This convertor is able to shape the spectrum of the error caused by the mismatch among its components. The hardware implementation is based on a simple, binary-weighted structure     

A/D conversion with imperfect quantizers

This paper analyzes mathematically the effect of quantizer threshold imperfection commonly encountered in the circuit implementation of analog-to-digital (A/D) converters such as pulse code modulation (PCM) and sigma-delta (/spl Sigma//spl Delta/) modulation. /spl Sigma//spl Delta/ modulation, which is based on coarse quantization of oversampled (redundant) samples of a signal, enjoys a type of self-correction property for quantizer threshold errors (bias) that is not shared by PCM. Although "classical" /spl Sigma//spl Delta/ modulation is inferior to PCM in the rate-distortion sense, this robustness feature is believed to be one of the reasons why /spl Sigma//spl Delta/ modulation is preferred over PCM in A/D converters with imperfect quantizers. Motivated by these facts, other encoders are constructed in this paper that use redundancy to obtain a similar self-correction property, but that achieve higher order accuracy relative to bit rate compared to classical /spl Sigma//spl Delta/. More precisely, two different types of encoders are introduced that exhibit exponential accuracy in the bit rate (in contrast to the polynomial-type accuracy of classical /spl Sigma//spl Delta/) while possessing the self-correction property.     

Current-mode cyclic A/D conversion technique

A cyclic analogue-to-digital (A/D) conversion technique using current copiers is described. The technique requires two steps per bit conversion. The resulting digital codes are insensitive to process component mismatches. This method can be applied to both the cyclic and the pipeline structure depending on the design requirements.<>     

Dual-mode pipeline A/D converter for direct conversion receivers

An embedded dual-mode 8 bit 1/15.36 MS/s CMOS pipeline A/D converter for 2G and 3G multimode direct conversion receivers in presented. Power dissipation is minimised by optimising the architecture and by utilising voltage reference circuitry and operational amplifiers, which are reconfigured between the narrow- and wide-band modes     

High-resolution A/D conversion in MOS/LSI

A new successive approximation analog-to-digital conversion technique compatible with most MOS process technologies is described. This technique combines a string of equal value diffused resistors and a binary ratioed capacitor array in a unique circuit configuration so that 12-bit monotonicity is achieved with only 8-bit ratio-accurate circuit elements. The comparator is realized by a chopper-stabilized amplifier to reduce the inherently high input offset voltages of MOS amplifiers. Typical performance characteristics taken from a sample of ICs are presented; 12-bit monotonic conversion with differential nonlinearity less than 1/2 LSB is completed in 50 /spl mu/s. The die area, less logic, is 12000 mil/SUP 2/. Because of assured 12-bit monotonicity, this converter should find applications of closed-loop control systems. It seems feasible to extend this technique to 14-bit resolution for use in applications such as digital audio systems.     

On a recursive A/D conversion technique

This letter focuses on a recursive method proposed by the author several years ago and now suitable for a system-level IC implementation. Some comments referring to the flexibility and operability of such a class of devices are also reported.     

Circuit techniques for achieving high speed-high resolution A/D conversion

A 12 bit, 25 /spl mu/s, analog-to-digital converter has been successfully integrated on two process-compatible junction-isolated chips. One chip contains a 200 ns digital-to-analog converter with reference, while the other contains the comparator, an I/SUP 2/L successive-approximation register, multiplexed three-state T/SUP 2/L output buffers, and a controller designed to interface directly to several common microprocessors. The authors describe several innovations which allow this degree of integration at the 12 bit accuracy level.     

A 5-GHz SiGe HBT return-to-zero comparator for RF A/D conversion

This paper presents a monolithic comparator implemented in a 0.5-μm SiGe heterojunction bipolar transistor (HBT) process. The SiGe HBT process provides HBT npn transistors with maximum f_T over 40 GHz and f_max over 55 GHz. The comparator circuit employs a resettable slave stage, which was designed to produce return-to-zero output data. Operation with sampling rates up to 5 GHz has been demonstrated by both simulation and experiments. The comparator chip attains an input range of 1.5 V, dissipates 89 mW from a 3-V supply, and occupies a die area of 407×143 μm². The comparator is intended for analog-to-digital (A/D) conversion of 900 MHz RF signals     

A flip-flop sensor array with on-spot A/D conversion

A two-dimensional optical flip-flop sensor array, consisting of an 8×8 matrix of flip-flop sensors integrated in one chip together with sense amplifiers and access selection circuitry, is discussed. A flip-flop sensor contains two phototransistors, one of which is covered over the aluminum while the other is exposed to light. Each flip-flop senses the light intensity and converts it to a series of ones and zeros. It is operated by turning the supply current on and off with a high frequency. During the absence of light the flip-flop is totally symmetrical and the number of ones and zeros is equal. Light causes an asymmetry in the flip-flop that changes the ratio of ones and zeros. A fully digital output is obtained by counting the number of ones. A triangle-wave voltage is applied to the flip-flop to vary its threshold. The device showed that a large array of sensors with on-spot A/D (analog-to-digital) conversion can be realized using the flip-flop sensor technique     

Novel multiple reference voltage generation scheme for pipeline A/D conversion

A novel scheme for generating multiple reference voltages for pipeline A/D conversion is proposed. The basic idea is to develop the required reference voltages by summing the voltages from two reference voltage banks. This scheme has potential for high-speed conversion. Further, the architecture of the resistor network which forms the two voltage banks, offers a wide trade-off in power dissipation and speed while requiring a small chip area.<>     

高速光模-数转换关键技术

采用光子学技术实现模-数(A/D)转换,可克服电子瓶颈的限制,大幅度提高采样率,满足宇宙探测、超宽带雷达等应用需求.研究了基于光纤的高速光A/D转换系统,针对被动锁模光纤激光器重复频率低的不足,提出了采用波分复用(WDM)和光时分复用(OTDM)相结合来提高采样脉冲频率的方法,阐述了其中的关键技术,实现了83.97 Gs/s高速时间-波长交织光采样脉冲;分析了光纤色散对时钟抖动、进而对系统有效比特教的影响,给出了模拟计算结果;提出了减少色散影响的方法,通过自行研制的高精度机械式微拉伸器进行了色散补偿.实验结果验证了其有效性.     

采用电压复位技术的像素级模数转换器

This paper presents a 50 Hz 15-bit analog-to-digital converter(ADC) for pixel-level implementation in CMOS image sensors.The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets.The core circuit for charge/pulse conversion is specially optimized for low power,low noise and small area.An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification.The measurement result shows a standard deviation of 1.8 LSB for full-scale output.The ADC has an area of 4545 m2 and consumes less than 2 W in a standard 1P-6M 0.18 m CMOS process.