On the Implementation of an Analog ATPG: The Linear Case

A self-testing algorithm in which post-test simulation with failure bounds is employed, has been proposed. Based on this self-testing algorithm, an analog Automatic Test Program Generation (ATPG) for linear circuits or systems is being developed. The AATPG code is subdivided into off-line and on-line components while the actual test can be run in either a fully automatic mode or interactively.     

Data acquisition system for the VENUS detector at TRISTAN

A data acquisition system for the VENUS detector at the TRISTAN electron-positron collider is presented. The whole system of the VENUS detector consists of nine different kinds of principal detectors, and the total number of electronics channels of the system reaches about 30 000. A FASTBUS system was introduced as the main data path and the TKO and the CAMAC standard have also been utilized for the frontend electronics. A FASTBUS interface to an on-line computer (VAX11/780), simplex segment interconnect and many data acquisition modules were developed. Most of the data are analyzed in a VAX cluster system in real time. Data logging is done in a main frame computer (FACOM M382) by using an automatic loading cartridge tape subsystem.     

Error analysis of digital phase measurement of distorted waves

An analysis of errors associated with the digital measurement of phase angle between two signals, one of which may be distorted by a harmonic, is presented. All the results were found by running a simulation program on a VAX 11/780 computer. The results are very useful for the users of the phase meters. This technique may introduce large errors for some particular types of input waves. The main purpose of this work is to explain how large the error could be under certain conditions on the input waves     

一种新的模拟电路故障模糊集确定算法

提出了一种在模拟电路故障诊断中故障类模糊集的确定算法．该算法基于测前仿真法,不但同时适用于线性电路和非线性电路,而且可以确定元件模糊组以外的故障类模糊集．算法利用电路仿真故障特征数据计算故障的类间差异矩阵,从而完成故障类模糊集的确定．计算示例验证了该算法的有效性．     

Flower Pollination Heuristics for Nonlinear Active Noise Control Systems

Abstract In this paper, a novel design of the flower pollination algorithm is presented for model identification problems in nonlinear active noise control systems. The recently introduced flower pollination based heuristics is implemented to minimize the mean squared error based merit/cost function representing the scenarios of active noise control system with linear/nonlinear and primary/secondary paths based on the sinusoidal signal, random and complex random signals as noise interferences. The flower pollination heuristics based active noise controllers are formulated through exploitation of nonlinear filtering with Volterra series. The comparative study on statistical observations in terms of accuracy, convergence and complexity measures demonstrates that the proposed meta-heuristic of flower pollination algorithm is reliable, accurate, stable as well as robust for active noise control system. The accuracy of the proposed nature inspired computing of flower pollination is in good agreement with the state of the art counterpart solvers based on variants of genetic algorithms, particle swarm optimization, backtracking search optimization algorithm, fireworks optimization algorithm along with their memetic combination with local search methodologies. Moreover, the central tendency and variation based statistical indices further validate the consistency and reliability of the proposed scheme mimic the mathematical model for the process of flower pollination systems.     

模糊自适应滤波的主动控制方法研究

由于主动控制中广泛使用的自适应滤波 - x L MS算法只适用于线性控制问题 ,针对一些非线性问题 ,本文提出利用一种非线性自适应滤波方法——基于模糊逻辑系统的自适应滤波方法来解决一类参考信号与外扰呈非线性函数关系的前馈主动控制问题。仿真结果表明 ,该模糊自适应滤波器优于线性滤波器的控制效果     

Controlled-source analogous circuits and SPICE models forpiezoelectric transducers

Transmission line analogous circuits for piezoelectric transducers are developed which employ controlled sources rather than the traditional transformer to model the coupling between the electrical and the mechanical systems. A novel method is used to derive each model that consists of adding a term that is equal to zero to one of the device electromechanical equations. When this is done, it is shown that the equations can be cast into the form of the familiar telegraphist's equations for the voltage and current on an electrical transmission line. The circuits are derived for both the thickness-mode piezoelectric transducer and the side-electrode bar piezoelectric transducer. SPICE models of the analogous circuits are presented and an example simulation is given     

Computer simulation of the transmission of modulated signals through linear analog circuits using fast Fourier transforms

An algorithm is proposed for computing transformations of modulated signals in linear circuits by the spectrum method and by applying fast Fourier transforms. The algorithm computes transformations of oscillations with complex modulation and large angle modulation indexes in analog circuits. The accuracy of the proposed method is discussed. A program is described for analyzing modulated oscillations in linear selective circuits that complements the known electronic circuit simulation programs. Translated from Izmeritel'naya Tekhnika, No. 8, pp. 38–40, August, 1998.     

Switched Reluctance Machines as Three-Phase AC Autonomous Generator

The operation of the switched reluctance machine as an autonomous three-phase ac generator is considered. Two circuits are proposed. The generator circuit consists of only capacitors and load supplementary to the generator, but does not contain any power supply. Theoretical approaches for simulation of the three-phase autonomous switched reluctance generator are presented. The influence of the high harmonics in the phase current on the power output is discussed. Experimental and simulation results are presented     

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.     

A two-step methodology for CMOS VLSI reliability improvement: Step one

Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck-at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two-step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre-SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.     

Computer aided design of quartz crystal oscillators

The latest development of a simulation program designed for quartz crystal oscillator analysis is presented in this paper. The simulator being developed uses the full nonlinear Barkhausen criterion method. It consists of finding the frequency ω₀ and the amplitude u₀ which nullify both the real and imaginary parts of a characteristic complex polynomial P(u,jω) describing the oscillator behavior. Most of the nonlinearities come from the amplifying transistor described by using large signal admittance parameters y(u) obtained by means of an analog circuit simulator (SPICE). This paper presents the method used to derive and code the characteristic polynomial coefficients. This method has been successfully implemented for a Colpitts oscillator and is currently being used to build an oscillator library covering the most widely used structures. The validity and the predictive power of the model have been checked experimentally and the comparison between experimental results and simulation is presented and discussed     

Synchronous generator third-order model parameter estimation using online experimental data

A method to estimate the dynamic parameters of the commonly used third-order d-q model of a synchronous generator, based on measured electrical power, reactive power, terminal voltage, field current, field voltage and rotor angle following a small perturbation of the field voltage, is described. The parameters are estimated from two newly developed nonlinear functions for electrical power and terminal voltage by using a nonlinear least squares (NLS) algorithm. Results of simulation studies and experimental data collected from an 80 MVA, 10.5 kV generator show the efficacy of the proposed method and also reveal that the proposed method is valid for a wide range of operating conditions. For cases where rotor angle is not available, a new method for rotor angle estimation is also proposed.     

An efficient and novel FDTD method based performance investigation in high-speed current-mode signaling SWCNT bundle interconnect

Carbon nanotube (CNT) has emerged as the most extensively researched area in nanoscience and amongst the frontrunners in co-triggering the nanotechnology revolution. Single-wall CNT (SWCNT) bundle is a part of CNT family and has been proposed as the future nano-wires in integrated circuits. The present paper analyzes the performance of SWCNT bundle interconnect with high-speed current-mode signaling (CMS) scheme using efficient finite-difference time-domain (FDTD) method. For the first time, FDTD based method is explored for modeling CMS SWCNT bundle interconnect incorporating practical CMOS driver gate. The CMOS gate is characterized by n^th power-law model. The stability of FDTD method is ascertained by Courant condition. The proposed FDTD based method is efficient and can be used for performance analyses of future nano-wire SWCNT bundle as well as conventional copper interconnects. At the same time, this method is applicable for both traditional full-voltage swing voltage-mode signaling (VMS) and remarkable low-voltage swing CMS schemes. The various analyses in the paper reveal that CMS SWCNT bundle interconnect has higher edge over CMS copper interconnect in terms of smaller delay, lesser crosstalk induced delay and noise. The proposed analytical FDTD based method is validated using Tanner-SPICE EDA simulation tool. The maximum error between the FDTD and SPICE for the transient response in CMS SWCNT bundle interconnect for 32 nm technology node is within 3%.     

Automatic tuning method for the design of supplementary damping controllers for flexible alternating current transmission system devices

The design of supplementary damping controllers to mitigate the effects of electromechanical oscillations in power systems is a highly complex and time-consuming process, which requires a significant amount of knowledge from the part of the designer. In this study, the authors propose an automatic technique that takes the burden of tuning the controller parameters away from the power engineer and places it on the computer. Unlike other approaches that do the same based on robust control theories or evolutionary computing techniques, our proposed procedure uses an optimisation algorithm that works over a formulation of the classical tuning problem in terms of bilinear matrix inequalities. Using this formulation, it is possible to apply linear matrix inequality solvers to find a solution to the tuning problem via an iterative process, with the advantage that these solvers are widely available and have well-known convergence properties. The proposed algorithm is applied to tune the parameters of supplementary controllers for thyristor controlled series capacitors placed in the New England/New York benchmark test system, aiming at the improvement of the damping factor of inter-area modes, under several different operating conditions. The results of the linear analysis are validated by non-linear simulation and demonstrate the effectiveness of the proposed procedure.     

SPICE macromodel and CMOS emulator for memristors

In this paper, a new SPICE macromodel and CMOS emulator for memristors are proposed and verified to fit to the memristor's model equation very well in the entire range of memristor's resistance from the RESET state to the SET state. Compared with the memristor's model equation, average percentage errors in the new SPICE macromodel and in the 4-bit CMOS emulator are less than 0.5% and 0.9%, respectively. In addition, the CMOS emulator for memristors which can be implemented by a CMOS circuit will be very useful to design and verify various peripheral circuits for memristor applications particularly when the memristor fabrication process is not ready.