Simulation for capacitance correction from Nyquist plot of complex impedance–voltage characteristics

The impression of series resistance on unipolar semiconductor device’s capacitance–voltage spectrum is discussed by conventional impedance and admittance analysis, and it is shown that series resistance may cause large errors in capacitance–voltage data. It is shown that the existence of such errors can be deduced from suitable complex impedance measurement obtained during the capacitance–voltage measurement process and this information can be used to correct the distorted capacitance values. A theoretical analysis and computer simulation are presented in order to illustrate the nature of the problem and the technique by which accurate depletion region capacitance can be obtained.     

Integrated overcurrent protection system for class-D audio power amplifiers

A fully integrated overcurrent protection system is presented suitable for application in integrated class-D audio power amplifiers. Accurate overcurrent detection is used based on parallel measurement of the voltage drop across the DMOS power transistors. A logic circuit enables continuous current limiting during overload situations. Actual short circuits can be distinguished from load impedance minima using a simple short-circuit discrimination method.     

High-Efficiency Broadband Parallel-Circuit Class E RF Power Amplifier With Reactance-Compensation Technique

Class E amplifier offers high efficiency approaching 100% for an ideal case. This paper introduces a first practical implementation of a novel broadband class E power amplifier design combining a parallel-circuit load network with a reactance compensation technique. The novel broadband parallel-circuit class E load network using reactance compensation technique has been discussed based on theory and its experimental verification. A proper guidelines method of designing a high-efficiency broadband class E power amplifier with an LDMOS transistor until the final prototype measurement and optimization will be discussed. In the measurement level, the drain efficiency of 74% at an operating power of 8 W and power flatness of 0.7 dB are achieved across a bandwidth of 136-174 MHz. The efficiency result is the highest result for VHF broadband frequency to date with a low supply voltage of 7.2 V. Simulations of the efficiency, output power, drain voltage waveform, and load angle (impedance) were verified by measurements and good agreements were obtained.     

Small-Signal Impedance Measurement of Power-Electronics-Based AC Power Systems Using Line-to-Line Current Injection

Naval ships as well as aerospace power systems are incorporating a greater degree of power electronic switching sources and loads. Although these components provide exceptional performance, they are prone to instability due to their high efficiency and constant power characteristics that can exhibit negative impedance nature at certain frequencies. When designing these systems, integrators must consider the impedance versus frequency at an interface (which designates source and load). Stability criteria have been developed in terms of source and load impedances for both dc and ac systems, and it is often helpful to have techniques for impedance measurement. For dc systems, the measurement techniques have been well established. This paper introduces a new method of impedance measurement for three-phase ac systems. By injecting an unbalanced line-to-line current between two lines of the ac system, all impedance information in the traditional synchronous reference frame $d{-}q$ model can be determined. For medium-voltage systems, the proposed technique is simpler and less costly than having an injection circuit for each phase. Since the current injection is between only two phase lines, the proposed measurement device can be used for both ac and dc interfaces. Simulation and laboratory measurements demonstrate the effectiveness of this new technique.      

A Low-Power Self-Forward-Body-Bias CMOS LNA for 3–6.5-GHz UWB Receivers

A low-power low-noise amplifier (LNA) implemented in 0.18 $mu$m CMOS technology utilizing a self-forward-body-bias (SFBB) technique is proposed for UWB low-frequency band system. By using the SFBB technique, it reduces supply voltage as well as saves additional bias circuits, which leads to low power consumption of 4.5 mW with low supply voltage of 1.06 V for two drain-to-source voltage drops. The complementary architecture and direct coupling technique between the first two stages also save bias circuits. The measurement result shows that the proposed LNA presents a maximum power gain of 16 dB with a good input impedance matching (${rm S}11 < - 12$ dB) and an average noise figure of 2.65 dB in the frequency range of 3–6.5 GHz.      

Power Filter Insertion Loss Evaluated in Operational-Type Circuits

Insertion losses of several different manufacturers' 100-ampere power filters were measured in the frequency range 100 Hz to 2 MHz and at a range of power current loads utilizing a newly developed current injection probe. The measurements were made using a technique which, in compliance with IEEE measurement standards, provides a constant voltage source in a filter-in filter-out measurement circuit, where source and load impedance parameters are known. Theoretically derived curves for the power filters installed in circuits with complex source and load impedance are compared to measured curves. Theoretically derived curves for current or voltage attenuation are also compared to insertion loss curves. Significant departures from the MIL-STD-220A specification curves were obtained using this new current injection probe measurement method. Strong saturation effects were found with several of the filters. Wide passband excursions were obtained as predicted by the theoretical treatment. The new measurement technique is described in terms of its relation to IEEE standard definitions of insertion loss. A discussion is given of present and proposed methods in relationship to what is felt is the most useful means of describing a filter's operational characteristics.     

A new approach for direct observation of base width modulation invertical bipolar transistors

A new DC measurement technique that allows direct observation of the forward and reverse Early effects is described. The technique employs a special test structure and is used to accurately determine the Early voltage parameters in the Gummel-Poon model. The improvements provided by this method over existing parameter extraction techniques are realized by using a direct measurement of the normalized base charge as a function of the emitter and collector junction biases. The new technique described here allows the Early voltage parameters to be extracted as a function of applied bias in a straightforward manner and is suitable for high volume measurements for statistical characterization and for process monitoring in an industrial setting     

Calibration Technique for Maximum Power Harvest of Passive Wireless Microsystems

A calibration technique for maximizing radio-frequency power harvest of passive wireless microsystems with a step-up transformer is proposed. We show that both the impedance and resonant frequency of the step-up transformer matching network can be adjusted by varying the capacitance of a shunt varactor placed at the secondary winding of the transformer to maximize power transfer from the antenna to the transformer and the output voltage of the transformer subsequently the power efficiency of the voltage multiplier. A low-power current-mode tuning technique and a maximum peak amplitude detection technique to allocate the optimal tuning capacitance at which the maximum power harvest exists are introduced. The transformer matching network has been designed in IBM CMRF8SF 130-nm 1.2-V CMOS technology, and its performance is validated using both simulation and on-wafer measurement results.     

Technique for measurement of powerline impedances in the frequencyrange from 500 kHz to 500 MHz

A method for measuring power line impedances using two current probes is examined. This method is characterized by good isolation of the measurement equipment from the power line voltage and by the capability of measuring power line impedances between any pair of power-plug terminals. The use of this two-current probe method with the model described is effective in measuring power line impedances from 0.5 MHz to 100 MHz. Using purely resistive loads for calibration, the error is less than 5% for frequencies below 100 MHz, and less than 20% for frequencies between 100 MHz and 500 MHz. The error in an impedance measurement increases with the magnitude of the load impedance     

Measurement of low impedance on chip power supply loop

A new method of measuring the high frequency self-impedance and transfer impedance of a microprocessor's power supply loop is proposed. The method is based on measurement of the on-chip voltage in response to a predetermined stimulus. Two methods of the stimulus current generation are presented: running a set of computer instructions and toggling clock frequency while the system is in reset.     

A Low-Frequency Current Probe System for Making Conducted Noise Power Measurements

The two current probe technique of measuring conducted radio-frequency interference is a radical departure from conventional measurement techniques. The technique evolved from a dissatisfaction with present techniques, due to the lack of sufficient information obtained from measurements concerning the source of the interference. Normally, the wires concerned when testing for conducted interference are 60-Hz power lines of the two conductor type. If a pair of conductors comprising a power cord is considered as a transmission line, the factors which determine its performance at radio frequencies are primarily the wire length and loading. In practice, power lines do not have readily described configurations, which makes a transmission-line analysis extremely difficult. As a result, no attempt to analyze the situation is made at all. Usually, a line impedance stabilization network (LISN) is inserted into the line and the noise voltage developed is measured across a 50-ohm internal resistor which is effectively placed across the line. Thus, the only information obtained is a noise voltage which existed across a resistor at the time of measurement, but is nonexistent after the test. The noise voltage existing across the line after the LISN has been removed remains unknown. As a matter of fact, it cannot even be calculated, since the line characteristics are unknown. Thus insufficient information is the reason for pursuing the current probe techniques. The two current probe technique of measuring conducted interference overcomes the limitations of the LISN technique by supplying more information about the line.     

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13- $muhbox{m}$ standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 $hbox{mm}^{2}$.      

基于STM32的自动量程电压表的设计

本设计能够精确的测量直流电压、交流电压,具有测量精度高,抗干扰能力强等特点。整个系统可以用一块9V电池供电,实现了低功耗和便携功能。交流测量是用AD637真有效值转换芯片将交流信号转换成直流电压后测量;用带钳位保护的反向放大器进行输入电压转换,实现了10MΩ的输入阻抗和高安全性。电路中关键器件采用TI公司的精密运算放大器OPA07和仪表放大器INA128,实现了高精度的测量;ADC采用STM32f103ZET6片内自带的12位AD,实现了低功耗,量程自动切换功能。     

Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

An ultra-wideband (3.1-10.6 GHz) low-noise amplifier using the 0.18 μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW (without output buffer for measurement) with a 1.8 V power supply and occupies 0.88 mm2.     

Phase retrieval from impedance amplitude measurement

In this letter, we propose a numerical method for computing the phase spectrum of impedance. The developed method is based on the maximum entropy model (MEM) and enables one to retrieve the phase spectrum directly from an impedance amplitude spectrum. The validity of the method is tested with an input impedance measurement of a distribution transformer in the frequency band 100 kHz-30 MHz, where both the amplitude and the phase spectrum of the impedance are measured. According to the tests carried out, the method is useful and it may be applied, for example, in the research of active filters, power line communication, and electromagnetic interference.     

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer’s operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer’s operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.     

A Low Frequency Current Probe System for Making Conducted Noise Power Measurements

A technique for accurately measuring conducted radio frequency interference has been developed at the U.S. Naval Civil Engineering Laboratory. The technique involves the use of two current probes simultaneously to determine the impedance levels of the lines or equipment under measurement. The noise currents of the lines or electrical equipment are measured directly using one of the two probes. Knowing the noise currents and the impedances through which it flows provides the necessary information for computing noise voltages and noise power. Further, it allows prediction of the noise power delivered by the measured device into any known impedance connection. The bandwidth covered by this technique is 20KC-30mc. This range is covered by two instruments, the first covers 20KC-2mc and the second 2mc-30mc. The high frequency instrument has been described before and will not be discussed here. The low frequency instrument is new and has several unique features. The main feature being a direct read out of both the impedance magnitude and the phase angle of the system being measured. This is accomplished by transistorized circuits which drive two front panel meters, one for impedance magnitude and one for phase angle and its polarity. By providing the phase information it is possible to specify the noise observed in terms of noise power. This technique removes the many ambiguities which are normally associated with conducted noise measurements using line impedance stabilization networks.     

Implementation and Test of an Online Embedded Grid Impedance Estimation Technique for PV Inverters

New and stronger power quality requirements are issued due to the increased amount of photovoltaic (PV) installations. In this paper different methods are used for continuous grid monitoring in PV inverters. By injecting a noncharacteristic harmonic current and measuring the grid voltage response it is possible to evaluate the grid impedance directly by the PV inverter, providing a fast and low-cost implementation. This principle theoretically provides an accurate result of the grid impedance but when using it in the context of PV integration, different implementation issues strongly affect the quality of the results. This paper also presents a new impedance estimation method including typical implementation problems encountered, and it also presents adopted solutions for online grid impedance measurement. Practical tests on an existing PV inverter validate the chosen solution.     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

Impedance spectroscopy of human erythrocytes: system calibration,and nonlinear modeling

The authors present an impedance measurement method, the cell embedding technique, for human erythrocytes, and an accurate calibration procedure for a four-electrode impedance measurement system that gives reliable results over a wide frequency range-1 Hz to 10 MHz. To achieve high sensitivity, the cells are embedded in the pores of a Nuclepore filter. The calibration procedure assumes that the measurement system is linear and require measurement of three reference impedances. The reliability of the procedure is demonstrated with various RC circuits. Its application to the bio-impedance measurement system eliminates a quasi-dispersion in the high-frequency range and increases the bandwidth at both the low- and high-frequency ends of the range by about a decade. The experimental data are fitted to, an equivalent circuit model of the impedance of the embedded cells. The impedance spectra display constant-phase-angle (CPA) characteristics, which are used to describe the AC response of the interface between the cell surface, and the external electrolyte solution. Such a CPA element may be related to fractal character of the interface