Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 Vsupply voltage regime

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 μm BiCMOS process. The delay and power dissipation of several NAND configurations have been compared. The new circuits offer delay reduction between 40 and 66% over CMOS in the range 1.2-3.3 V supply voltage. The minimum fanout at which the new circuits outperform CMOS gate is 5, which is lower than that of other gates particularly for sub-2.5 V operation     

A delay model and optimization method of a low-power BiCMOS logiccircuit

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-μm BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

Low-voltage adders for power-efficient arithmetic circuits

This paper presents the results of a study of alternative adder architectures, a full-swing Bipolar Double Pass-Transistor adder, a new full-swing BiNMOS adder, a reduced-swing Bipolar Double Pass-Transistor adder and a reduced-swing Double Pass-Transistor BiNMOS adder, that outperform a standard CMOS adder up to three times in power-efficiency at supply voltages 1.5–3 V. The Bipolar Double Pass-Transistor adder is more power-efficient than a standard CMOS adder even at a fanout of 1. All remaining proposed adders have a lower crossover capacitance with a standard CMOS adder than the previously reported low-voltage adders. Circuits were designed and fabricated in 0.8 μm BiCMOS technology.     

Evaluation of delay-time degradation of low-voltage BiCMOS based ona novel analytical delay-time modeling

The degradation of delay time of totem-pole BiCMOS, CBiCMOS, and BiNMOS circuits by supply voltage reduction is evaluated by a novel delay-time model. It has been found that base-collector capacitance plays a greater role in determining the delay time than other parasitic capacitances in BiCMOS circuits. It is concluded that when the input signal swings fully from zero to the supply voltage, the minimum supply voltage to guarantee high-speed operation over CMOS circuits is almost the same for the three kinds of BiCMOS circuits. When the input swing is reduced by the base-emitter voltage, however, BiNMOS and CBiCMOS circuits can operate on a lower supply voltage than totem-pole BiCMOS circuits     

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

Design of a 1.5 V full-swing bootstrapped BiCMOS logic circuit

A low voltage full-swing BiCMOS bootstrapping technique that allows the design of BiCMOS logic circuits at supply voltages down to 1.5 V is presented. This is the first 1.5-V design technique that does not require complementary bipolar devices. The technique is shown to have significant advantages over existing low voltage BiCMOS logic designs in sub-3 V operation. Inverter gates fabricated using a 0.8-μm technology were operated at 150 MHz with a supply voltage of 1.5 V. Implementation of this technique on dynamic logic is also demonstrated and experimental results match closely with simulation     

Full-swing BiCMOS logic circuits with complementaryemitter-follower driver configuration

Various full-swing BiCMOS logic circuits with complementary emitter-follower driver configurations are described. The performance of the circuits is demonstrated in a 1.2 μm complementary BiCMOS technology with a 6 GHz n-p-n and a 2 GHz p-n-p transistor. For the basic circuit, gate delay (fan-in=2, fan-out=1) is 366 ps and driving capability is 288 ps/pF at 4 V. Delay-power tradeoffs that depend on characteristics of the clamping diode between two base nodes of the complementary emitter-follower driver, parasitic capacitances at the two base nodes, and a technique that can be used to achieve full swing have been identified for these circuits. These circuits show leverage over the conventional BiCMOS circuit for reduced power-supply voltages     

A bootstrapped bipolar CMOS (B2CMOS) Gate forlow-voltage applications

This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing operation down to 1.1 V supply voltage. The proposed B²CMOS uses a conventional (noncomplementary) BiCMOS process. HSPICE simulations have been used to compare the B²CMOS to CMOS, BiNMOS, and BS-BiCMOS for sub-0.5 μm BiCiMOS technologies. Simulation results have shown that the B²CMOS gate outperforms CMOS, BiNMOS, and BS-BiCMOS gates at 3 V and below. The crossover capacitance/fanout of the B²CMOS gate is 100 fF (i.e., fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B²CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V     

Noncomplementary BiCMOS logic and CMOS logic for low-voltage,low-power operation-a comparative study

This paper presents results of a comprehensive comparative study of six bipolar complementary metal-oxide-semiconductor (BiCMOS) noncomplementary logic design styles and two CMOS logic styles for low-voltage, low-power operation. These logic styles have been compared for switching power consumption and power efficiency (power-delay product). The examination offers two alternative approaches never used in other comparative studies. First, all BiCMOS-based styles are compared to low-power CMOS styles as opposed to a single conventional static CMOS style. Second, a low-power methodology has been used as opposed to performance methodology referred to in the previous logic comparisons. The styles examined are bootstrapped BiCMOS, bootstrapped full-swing BiCMOS, bootstrapped bipolar CMOS, Seng-Rofail's bootstrapped BiCMOS, modified full-swing BiCMOS, dynamic full-swing BiCMOS, double pass-transistor CMOS, and inverter-based CMOS. These design styles have been compared at various power supply voltages (0.9-3 V), with various output load capacitances (0.1-1 pF) at the frequency 50 MHz and temperature 27°C. The results clearly show which logic style is the most beneficial for which specific conditions     

Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossoverbelow 2.5-V supply

The authors discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. MBiCMOS maintains a measured delay and power-delay advantage over CMOS into the 2-V supply range, in a simple four-device gate that does not require any change in the standard BiCMOS processing sequence. In a 2-μm technology, MBiCMOS outperforms CMOS down to a 2.6-V supply. Gates designed for fabrication in a 0.5-μm technology and simulated using measured device parameters indicate that MBiCMOS can be used to extend the performance crossover voltage to below 2 V in the submicrometer regime. A full-swing version of the MBiCMOS gate (FS-MBiCMOS) is introduced. Simulations of 2-μm gates show FS-MBiCMOS/CMOS performance crossover voltages of 2.2 V     

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

Applications of composite BiCMOS transistors

The concept of the composite CMOS transistor is generalised and extended to include both, composite bipolar and composite BiCMOS transistors. Two versions of the BiCMOS device and its applications in some linear circuits to reduce supply voltage requirements and increase effective transconductance are discussed. Experimental results using transistor arrays are presented.<>     

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

高速低压低功耗BiCMOS逻辑电路及工艺技术

介绍了几种高开关速度、低电源电压等级，低功耗的BiCMOS逻辑门电路，并分析了它们的工作原理及其工艺技术情况。结果表明，这些电路的电源电压可达到2．0V以下，而且信号传输延迟较小，有的还实现了全摆幅输出，因而它们可用于便携式电子设备和其它VLSI和ULSI新品等场合。