基于DVI双链路的超大分辨率亮度校正系统设计

具备亮度校正功能的DVI-DVI处理器被应用到LED大屏幕显示,可以较好的解决工程上为了增加或升级亮度校正功能而更换显示控制系统的问题.但是DVI-DVI处理器的动态内存读取频率较低,不能发挥DVI双链路的数据传输性能.本文通过对动态内存中待读取的校正参量按照特定算法进行重组和压缩,将动态内存的等效读取频率从266MHz提高到330MHz,实现DVI双链路传输对超大分辨率的LED显示屏进行有效的亮度校正.     

液晶电视亮度感应自动控制的设计

文章对液晶电视亮度感应自动控制存在的问题进行了深入探讨,并提出了对应的改进和防范措施.通过亮度感应器,采集到周围环境的亮度；进行多次采样自动校正算法,减少外界环境亮度变化的干扰,得到稳定的亮度；通过模拟迟滞比较算法,减少亮度忽亮忽暗的变化,设定稳定的控制液晶面板背光的脉宽调制信号；由脉宽调制信号对液晶而板背光进行调整得...     

基于配准的红外焦平面阵列条纹非均匀性校正

条纹非均匀性是线扫红外焦平面阵列和非制冷凝视型红外焦平面阵列成像系统中一种特殊的固定图案噪声.分析了其产生的原因,提出了一种基于亮度恒定假设和配准的条纹非均匀性校正算法.根据相邻两帧获得亮度均方误差函数,最后通过最小化全局亮度均方误差函数得到全局最优解作为非均匀性校正的参数.实验结果表明,该算法能够在几帧内达到较好的收...     

一种改善LED显示屏亮度均匀性的算法

基于显示屏控制技术与校正原理,提出了一种改善LED显示屏亮度均匀性的算法.通过CCD相机采集显示屏RGB图像,用数学形态学和模板匹配法确定灯点的位置并根据发光区域的灰度值计算其相对亮度,生成每个灯点的校正参数,用脉冲宽度调制控制灯点的亮度.实验结果表明提出的算法能有效改善显示屏的亮度均匀性,提高显示屏的显示质量并延长其使用寿命.     

CCD相机输出非均匀性线性校正系数的定标

宽幅CCD相机的输出非均匀性校正对获取高质量的遥感图像具有重要意义。通过分析造成CCD输出非均匀的原因,提出了基于辐射亮度反演的非均匀性线性校正概念。在已知的多种辐亮度照明下,采集相机每个像素的灰度值,利用最小二乘法建立像元灰度值与辐亮度的函数,求出像元的两项非均匀性校正系数——暗信号与响应度。实验结果表明:利用这两项校正系数进行相机非均匀性校正,改善效果明显。校正前图像的灰度值均方根偏差为1.3%,校正后为0.2%;从图像上看,校正前图像上的明暗条纹很明显,校正后得到消除。不仅如此,采用该校正方法还能够有效去除通道间输出非均匀性造成的整幅拼接图像的明暗不一致,得到均匀清晰的图像,结果令人满意。     

图像和视频亮度的自动调整

 对曝光不足的图像和视频进行亮度调整具有重要的理论研究意义和实际应用价值,本文提出一种基于梯度域操作的图像和视频亮度自动调整算法.对于静态图像,算法首先将图像分割为不同的亮度区域;然后分别计算各区域的亮度调整算子;最后通过求解一个梯度约束方程得到结果图像.我们进而将该算法延伸到视频,首先选取若干关键帧并使用上述图像亮度调整算法进行处理;然后对非关键帧进行分割并通过光流算法确定非关键帧上的分割区域与前后关键帧区域的对应关系;最后利用对应关系通过关键帧区域的亮度调整算子以及调整后的亮度指导非关键帧上各区域的亮度调整,并生成结果视频序列.本文算法可以有效处理空间和时间上曝光不足和不均的图像和视频,并能够较好地保持图像、视频的细节纹理信息,实验结果表明了算法的有效性.     

全彩LED显示屏局部修正快速算法

带有亮度逐点校正技术的LED屏更换点或模块后,需要修复全屏亮度一致性,针对其修复过程提出了一种局部亮度校正参量修正算法.采用该算法可快速计算出替换点或模块一致化校正参量,避免对全屏的重新校正.首先分析替换点像素的修正算法并更换模块的各个像素点的修正算法;然后通过PC机端软件定位处理点或模块,完成对更新点、模块的校正参量的局部修正过程;最后,利用该局部修正算法完成对LED显示屏亮度的一致化修正.经实测验证,局部修正方法与标准化方法在更新时间上,前者更快速和简便,且应用环境更广泛.     

基于亮度保持的子图像加权对比度增强

本文提出了一种有效的基于亮度保持对比度增强算法.利用BBHE(brightness preserving bi-histogram equalization)算法产生的两个子图像,对两个子图像进行加权求和,从而得到输出图像.同时,根据输入图像以及两个子图像的亮度均值,给出了一种基于亮度保持的权重系数的计算方法.实验结果表明,与其它亮度保持对比度增强算法相比,本文算法能够更准确地保持输入图像的亮度均值以及较好地实现对比度增强.另外,本文算法计算简单,能够满足实时性的要求.     

一种户外全彩LED显示屏亮度色度检测新方法

本文针对户外全彩LED显示屏的亮度和色度检测,提出了一种基于数字图像处理技术的检测新方法。首先对采集的LED显示屏图像进行预处理;然后通过水平与垂直投影来确定LED像素点的位置及亮度、色度的计算区域;最后记录亮度和色度不一致的LED像素点,以便进行后续校正。实验表明,该检测方法可实现对户外全彩LED显示屏亮度和色度的检测及后续的校正,大大提高LED显示屏的检测速度和显示质量。     

投影显示对美术馆参观者视觉舒适度影响的实验研究

搭建了美术馆实验环境,被观赏画作表面的照度为200 lx,采用LED光源的色温为3 300 K.改变投影仪的亮度和对比度参数,设定三种常用投影显示模式(模式1-亮度24.7 cd/m2,对比度12:1;模式2-亮度57.7 cd/m2,对比度20:1;模式3-亮度78.9 cd/m2,对比度24:1),分别对32名实验...     

VCO Design With On-Chip Calibration System

This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from$-$120.5 dBc/Hz to$-$118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the$K_ VCO$peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method.     

Application of orthogonal codes to the calibration of active phasedarray antennas for communication satellites

This work describes two algorithms designed for remote calibration of an N_c-element active phased-array antenna. These algorithms involve transmission of N⩾N_c time multiplexed orthogonal encoded signals. The received signals are coherently detected, accumulated in vector forms, and decoded with the inverse of the orthogonal encoding matrix. The unitary transform encoding (UTE) algorithm is most suited for digital beamforming as it requires additional encoding hardware for an analog implementation. The control circuit encoding (CCE) algorithm is ideally suited for analog beamformers as it requires no additional encoding hardware. The CCE method encodes phased-array elemental signals using a Hadamard matrix to control the switching of intrinsic phase shifter delay circuits. The UTE and CCE algorithms can reduce the average measurement integration times for the complete set of calibration parameters by ~N_c relative to the corresponding values for single-element calibration procedures. This is significant for satellite systems as calibration must be performed in a short enough time window that the process can be treated as being stationary. Proofs are given that the orthogonal codes satisfy the mathematical lower bounds for the asymptotic forms of calibration parameter estimation variances     

A digital processor for full calibration of pipelined ADCs

In this paper, a digital processor is presented for full calibration of pipeline ADCs. The main idea is to find an inverse model of ADC errors by using small number of the measured codes. This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital post-processing of the output bits. Some function approximation algorithms are tested and their performances are evaluated. To verify the algorithms, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with 1%-2% non-ideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency. The selected algorithm has been implemented on a Virtex-4 LX25 FPGA from Xilinx. The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 45.5 to 90 dB. The calibration processor also improves the integral nonlinearity of the ADC.     

基于流水线ADC的MDAC电容失配校准研究

针对MDAC中采样电容失配会降低ADC输出非线性性能的问题,提出了一种流水线ADC的前台数字校准技术。该前台数字校准技术利用ADC输出积分非线性的相对偏差提取误差,利用简单的多路选择运算单元进行误差补偿。在此基础上,采用Verilog HDL实现了RTL级描述并成功流片。仿真和测试结果表明,该校准算法能够提升ADC输出性能。     

一种流水线ADC后台数字校准算法的实现

介绍了一种改进的流水线模数转换器(ADC)数字校准算法,该算法使用了一个低速高精确度的参考ADC,同时结合了变步长的最小均方误差(LMS)滤波器校正流水线ADC的误差,从而提高校准速度和精确度。使用Verilog HDL语言设计了这种后台数字校准算法的寄存器传输级(RTL)电路,同时采取Simulink和Modelsim联合仿真的方法对电路进行验证。验证结果表明,与固定步长的校准算法相比,改进的校准算法拥有更快的收敛速度和更高的收敛精确度。     

CCD视频信号处理电路应用分析

首先对ＣＣＤ输出信号特性进行简要描述,然后针对ＣＣＤ信号存在复位噪声,对相关双采样法进行细致分析。为了改善视频图像,需要对图像的对比度和亮度进行调节,提出了可编程增益控制和数字化偏置控制方法。另外,对暗电子平自动和Ａ／Ｄ模数转换也进行比较深入的研究。ＸＲＤ４４６０是ＣＣＤ视频处理专用集成芯片,它包含了上面所述的所有功能。本文已成功地将ＸＲＤ４４６０ＣＣＤ视频信号处理与用芯片应用于遥感ＣＣＤ相机中,     

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).     

Digital Background-Calibration Algorithm for “Split ADC” Architecture

The “split ADC” architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.      

Radix-2 × 2 × 2 algorithm for the 3-D discrete Hartleytransform

The discrete Hartley transform (DHT) has proved to be a valuable tool in digital signal/image processing and communications and has also attracted research interests in many multidimensional applications. Although many fast algorithms have been developed for the calculation of one- and two-dimensional (1-D and 2-D) DHT, the development of multidimensional algorithms in three and more dimensions is still unexplored and has not been given similar attention; hence, the multidimensional Hartley transform is usually calculated through the row-column approach. However, proper multidimensional algorithms can be more efficient than the row-column method and need to be developed. Therefore, it is the aim of this paper to introduce the concept and derivation of the three-dimensional (3-D) radix-2 × 2 × 2 algorithm for fast calculation of the 3-D discrete Hartley transform. The proposed algorithm is based on the principles of the divide-and-conquer approach applied directly in 3-D. It has a simple butterfly structure and has been found to offer significant savings in arithmetic operations compared with the row-column approach based on similar algorithms     

Novel approaches to the measurement of arterial blood flow from dynamic digital X-ray images

We have developed two new algorithms for the measurement of blood flow from dynamic X-ray angiographic images. Both algorithms aim to improve on existing techniques. First, a model-based (MB) algorithm is used to constrain the concentration-distance curve matching approach. Second, a weighted optical flow algorithm (OP) is used to improve on point-based optical flow methods by averaging velocity estimates along a vessel with weighting based on the magnitude of the spatial derivative. The OP algorithm was validated using a computer simulation of pulsatile blood flow. Both the OP and the MB algorithms were validated using a physiological blood flow circuit. Dynamic biplane digital X-ray images were acquired following injection of iodine contrast medium into a variety of simulated arterial vessels. The image data were analyzed using our integrated angiographic analysis software SARA to give blood flow waveforms using the MB and OP algorithms. These waveforms were compared to flow measured using an electromagnetic flow meter (EMF). In total 4935 instantaneous measurements of flow were made and compared to the EMF recordings. It was found that the new algorithms showed low measurement bias and narrow limits of agreement and also out-performed the concentration-distance curve matching algorithm (ORG) and a modification of this algorithm (PA) in all studies.