SOI MOSFETI－V特性的计算机模拟

本文研究了ＳＯＩＭＯＳＦＥＴ的Ｉ－Ｖ特性，建立了一套模拟ＳＯＩ器件工作特性的解析模型，适用于不同的ＳＯＩ膜厚和各种前、背栅的偏置情况，在各种不同情况下由计算机自动选择适当模型进行拟合，该模型物理意义明确，计算简便快速，所用参数易于提取。     

Sub-100-nm vertical MOSFET with threshold voltage adjustment

Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L_DD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance     

Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has$sim$21% lower gate capacitance and lower$I_ off$by two orders of magnitude than a conventional saddle device under nearly the same$I_ on$. In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time$(CV/I)$by$sim$30% than the conventional recess channel device while keeping nearly the same$I_ off$.     

亚100nm多栅MOSFET的三维模拟

使用三维模拟软件对具有FINFET的多栅结构(主要是双栅和三栅)进行了模拟.对比了双栅和三栅的I-V特性.发现三栅的特性要优于双栅;减小FIN宽度(即两个侧栅之间的距离),双栅和三栅结构特性之间的差距变小.     

亚100nm多栅MOSFET的三维模拟

使用三维模拟软件对具有FINFET的多栅结构(主要是双栅和三栅)进行了模拟.对比了双栅和三栅的I-V特性.发现三栅的特性要优于双栅;减小FIN宽度(即两个侧栅之间的距离),双栅和三栅结构特性之间的差距变小.     

SOI LDD MOSFET的栅电流的模拟

本文介绍一种采用载流子总量方法分析ＳＯＩ ＭＯＳＦＥＴ器件特性及热载流子效应的数值模型。使用专用模拟程序ＬＡＤＥＳ７联解器件内部二维泊松方程、电子和空穴的连续性方案。ＬＡＤＥＳ７可用于设计和预测不同工艺条件、几何结构对器件性能的影响。该模型直接将端点电流、端点电压与内部载流子的输运过程联系在一起，可准确地模拟ＳＯＩ ＭＯＳＦＥＴ器件的特性并给出清晰的内部物理图象。本文给出了ＬＡＤＥＳ７软件模拟的部     

Monte Carlo Simulation of Nanoscale SOI MOSFETs

A comparative review is presented of the current research on the quantum-mechanical and classical Monte Carlo simulation of SOI MOSFETs. A quantum-mechanical simulation method is proposed whereby the energy of transverse channel quantization is represented by a correction term. A newly developed simulation program, called BALSOI, is outlined. A comparison is made between the results of a 2D classical Monte Carlo simulation and those obtained by the quantum-mechanical method. It is observed that the differences are much smaller than what one might expect. This finding is explained as due to the considerable effect of the space charge, which is mainly governed by the classical, longitudinal motion of carriers through the channel. An analytical formula is derived for the effect of channel quantization on the gate–channel capacitance. The strength of tunneling current through a short-channel transistor in the off state is considered.     

30-nm recessed S/D SOI MOSFET with an ultrathin body and a low SDE resistance

A novel ultrathin body SOI MOSFET with a recessed source-drain (S/D) structure is proposed to reduce the S/D extension (SDE) resistance and the feasibility on the proposed device is checked. A recessed buried oxide under the SDE regions is completely filled with the heavily doped polysilicon, which can lead to a low SDE resistance. A recessed S/D SOI MOSFET with 30 nm gate length and 5 nm thick undoped channel, was successfully fabricated and showed the good SCE immunities; little punch-through, the drain-induced barrier lowering of 140 mV/V, and the subthreshold slope of 79 mV/dec.     

低比导通电阻P埋层SOI双介质槽MOSFET

提出了一种带P型埋层的新型SOI双介质槽MOSFET.通过在SOI层底部引入P型埋层作为补偿,在耐压优化情况下增加漂移区的浓度,降低了比导通电阻.MEDICI TCAD仿真结果表明:在281 V击穿电压下,该结构的比导通电阻为4.6 mΩ·cm2,与不带P型埋层的结构相比,在达到同样耐压的情况下,比导通电阻降低了19％.     

A novel nanoscale SOI MOSFET with Si embedded layer as an effective heat sink

A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications.     

SOI/MOSFET Kink效应的模拟和分析

非全耗尽SOI/MOS晶体管由于存在“Kink效应”而限制了它的应用范围。本文考虑了沟道夹断区的碰撞电离和横向寄生晶体管效应,对浮置衬底SOI/nMOS晶体管的电流—电压特性曲线进行了理论计算,讨论了Kink效应的产生机理。计算结果与实验符合甚好。对器件参数的分析可以定性地指导抑制Kink效应的器件优化设计。     

深亚微米薄膜SOI MOSFET的二维数值模拟

本文介绍了适合于薄膜亚微米、深亚微米ＳＯＩＭＯＳＦＥＴ的二维数值模拟软件。该模拟软件同时考虑了两种载流子的产生－复合作用，采用了独特的动态二步法求解泊松方程和电子、空穴的电流连续性方程，提高了计算效率和收敛性。利用此模拟软件较为详细地分析了薄膜ＳＯＩＭＯＳＦＥＴ不同于厚膜ＳＯＩＭＯＳＦＥＴ的工作机理及特性，发现薄膜ＳＯＩＭＯＳＦＥＴ的所有特性几乎都得到了改善。将模拟结果与实验结果进行了对比，两者吻合得较好。     

带有P型埋层的新型双栅SOI MOSFET

本文提出一种超低比导通电阻(Ron,sp)可集成的SOI 双栅triple RESURF (reduced surface field)的n型MOSFET (DG T-RESURF)。这种MOSFET具有两个特点：平面栅和拓展槽栅构成的集成双栅结构(DG),以及位于n型漂移区中的P型埋层。首先, DG形成双导电通道并且缩短正向导电路径,降低了比导通电阻。DG结构在反向耐压时起到了纵向场板作用,提高了器件的击穿电压特性。其次, P型埋层形成triple RESURF结构 (T-RESURF),这不仅增加了漂移区的浓度,而且调节了器件的电场。这在降低了比导通电阻的同时提高了击穿电压。最后,与p-body区连接在一起的P埋层和拓展槽栅结构,可以显著降低击穿电压对P型埋层位置的敏感性。通过仿真,DG T-RESURF的击穿电压为325V,比导通电阻为8.6 mΩ?cm2,与平面栅single RESURF MOSFET(PG S-RESURF)相比,DG T-RESURF的比导通电阻下降了63.4%,击穿电压上升9.8%。     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合.     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应，在沟道源端一侧引入了高掺杂Halo结构．通过求解二维电势Poisson方程，为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型，并对其性能改进情况进行了研究．结果表明，新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应，并进一步提高载流子输运效率．新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱，但随Halo区长度非单调变化．解析模型与数值模拟软件MEDICI所得结果高度吻合．     

源区浅结SOI MOSFET的辐照效应模拟

研究了源区浅结的不对称SOIMOSFET对浮体效应的改善 ,模拟了总剂量、抗单粒子事件 (SEU)、瞬时辐照效应以及源区深度对抗辐照性能的影响 .这种结构器件的背沟道抗总剂量能力比传统器件有显著提高 ,并且随着源区深度的减小 ,抗总剂量辐照的能力不断加强 .体接触不对称结构的抗SEU和瞬时辐照能力优于无体接触结构和传统结构器件 ,这与体接触对浮体效应的抑制和寄生npn双极晶体管电流增益的下降有关     

源区浅结SOI MOSFET的辐照效应模拟

研究了源区浅结的不对称SOI MOSFET对浮体效应的改善,模拟了总剂量、抗单粒子事件(SEU)、瞬时辐照效应以及源区深度对抗辐照性能的影响.这种结构器件的背沟道抗总剂量能力比传统器件有显著提高,并且随着源区深度的减小,抗总剂量辐照的能力不断加强.体接触不对称结构的抗SEU和瞬时辐照能力优于无体接触结构和传统结构器件,这与体接触对浮体效应的抑制和寄生npn双极晶体管电流增益的下降有关.     

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.     

薄膜全耗尽应变Si SOI MOSFET特性模拟与优化分析

研究了应变Si沟道引入对薄膜全耗尽SOI MOSHET器件特性的影响,并分析了器件特性改进的物理机理.与传统的SOI MOSFET结构相比,器件的驱动电流和峰值跨导都有明显提高,对n-FET分别为21%和16.3%,对p-FET为14.3%和10%.应变si沟道的引入还降低了器件的阈值电压,这有益于集成电路中供电电压的降低和电路功耗的减小.另外,本文还对新结构中的Ge含量进行了优化分析,认为当Ge含量为30%时,器件有较好的电特性,而且不会增加器件制作的工艺成本.     

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿 (S/ D tunneling) ,采用 WKB方法计算载流子源漏隧穿几率 ,对薄硅层(硅层厚度为 1nm) DG(dual gate) MOSFETs的器件特性进行了模拟 .模拟结果表明当沟道长度为 10 nm时 ,源漏隧穿电流在关态电流中占 2 5 % ,在开态电流中占 5 % .随着沟道长度进一步减小 ,源漏隧穿比例进一步增大 .因此 ,模拟必须包括源漏隧穿 .