SOI MOSFETI－V特性的计算机模拟

本文研究了ＳＯＩＭＯＳＦＥＴ的Ｉ－Ｖ特性，建立了一套模拟ＳＯＩ器件工作特性的解析模型，适用于不同的ＳＯＩ膜厚和各种前、背栅的偏置情况，在各种不同情况下由计算机自动选择适当模型进行拟合，该模型物理意义明确，计算简便快速，所用参数易于提取。     

Sub-100-nm vertical MOSFET with threshold voltage adjustment

Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L_DD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance     

Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has$sim$21% lower gate capacitance and lower$I_ off$by two orders of magnitude than a conventional saddle device under nearly the same$I_ on$. In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time$(CV/I)$by$sim$30% than the conventional recess channel device while keeping nearly the same$I_ off$.     

SOI LDD MOSFET的栅电流的模拟

本文介绍一种采用载流子总量方法分析ＳＯＩ ＭＯＳＦＥＴ器件特性及热载流子效应的数值模型。使用专用模拟程序ＬＡＤＥＳ７联解器件内部二维泊松方程、电子和空穴的连续性方案。ＬＡＤＥＳ７可用于设计和预测不同工艺条件、几何结构对器件性能的影响。该模型直接将端点电流、端点电压与内部载流子的输运过程联系在一起，可准确地模拟ＳＯＩ ＭＯＳＦＥＴ器件的特性并给出清晰的内部物理图象。本文给出了ＬＡＤＥＳ７软件模拟的部     

Monte Carlo Simulation of Nanoscale SOI MOSFETs

A comparative review is presented of the current research on the quantum-mechanical and classical Monte Carlo simulation of SOI MOSFETs. A quantum-mechanical simulation method is proposed whereby the energy of transverse channel quantization is represented by a correction term. A newly developed simulation program, called BALSOI, is outlined. A comparison is made between the results of a 2D classical Monte Carlo simulation and those obtained by the quantum-mechanical method. It is observed that the differences are much smaller than what one might expect. This finding is explained as due to the considerable effect of the space charge, which is mainly governed by the classical, longitudinal motion of carriers through the channel. An analytical formula is derived for the effect of channel quantization on the gate–channel capacitance. The strength of tunneling current through a short-channel transistor in the off state is considered.     

30-nm recessed S/D SOI MOSFET with an ultrathin body and a low SDE resistance

A novel ultrathin body SOI MOSFET with a recessed source-drain (S/D) structure is proposed to reduce the S/D extension (SDE) resistance and the feasibility on the proposed device is checked. A recessed buried oxide under the SDE regions is completely filled with the heavily doped polysilicon, which can lead to a low SDE resistance. A recessed S/D SOI MOSFET with 30 nm gate length and 5 nm thick undoped channel, was successfully fabricated and showed the good SCE immunities; little punch-through, the drain-induced barrier lowering of 140 mV/V, and the subthreshold slope of 79 mV/dec.     

SOI/MOSFET Kink效应的模拟和分析

非全耗尽SOI/MOS晶体管由于存在“Kink效应”而限制了它的应用范围。本文考虑了沟道夹断区的碰撞电离和横向寄生晶体管效应,对浮置衬底SOI/nMOS晶体管的电流—电压特性曲线进行了理论计算,讨论了Kink效应的产生机理。计算结果与实验符合甚好。对器件参数的分析可以定性地指导抑制Kink效应的器件优化设计。     

A novel nanoscale SOI MOSFET with Si embedded layer as an effective heat sink

A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications.     

深亚微米薄膜SOI MOSFET的二维数值模拟

本文介绍了适合于薄膜亚微米、深亚微米ＳＯＩＭＯＳＦＥＴ的二维数值模拟软件。该模拟软件同时考虑了两种载流子的产生－复合作用，采用了独特的动态二步法求解泊松方程和电子、空穴的电流连续性方程，提高了计算效率和收敛性。利用此模拟软件较为详细地分析了薄膜ＳＯＩＭＯＳＦＥＴ不同于厚膜ＳＯＩＭＯＳＦＥＴ的工作机理及特性，发现薄膜ＳＯＩＭＯＳＦＥＴ的所有特性几乎都得到了改善。将模拟结果与实验结果进行了对比，两者吻合得较好。     

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.     

Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation

This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but computationally expensive (comprehensive Monte Carlo simulation), or overly simple (fixed corner design) and unable to capture crucial statistical variation concern, dominant in sub-100-nm designs. By mathematically combining the separate Monte Carlo simulation results of SRAM cells and each peripheral block, we show that the distribution of the SA input voltage can be estimated accurately in a case where fixed corner simulation underestimates by 19%. We also present the yield equation by combining the SA input voltage and the SA offset distribution, which can be used to choose the design point. In addition, yield sensitivities are derived from the yield data to make sure that the yield has good dependence to design variables.      

Si3N4栅MOS器件的隧穿电流模拟

随着MOS器件尺寸按比例缩小到亚100 nm时代,栅绝缘层直接隧穿(Direct Tunnel-ing,DT)电流逐渐增大.使用Si3N4材料作为栅介质,利用其介电常数高于SiO2的特性,可以在一定时期内有效地解决隧穿电流的问题.文章在二维器件模拟软件PISCES-II中首次添加了模拟高k材料MOS晶体管的器件模型,并对SiO2和Si3N4栅MOS晶体管的器件特性进行了模拟比较.     

Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET

We utilized a fully self-consistent quantum mechanical simulator based on the contact block reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO₂ gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.     

Device characteristics of a 30-V-class thin-film SOI power MOSFET

A 30-V thin-film SOI power MOSFET having a tungsten polycide gate with a linear gate topology has been fabricated at a practical device level. Its electrical characteristics were successfully demonstrated for the first time. The experimental device has 1010 unit cells and a total gate width of 4.04 cm, It has a specific on-resistance of 92 mΩ·mm² and breakdown voltage of 33 V. The device's various parasitic capacitance characteristics were measured and compared with those of a lateral power MOSFET fabricated on a bulk-silicon substrate     

SOI MOSFET structure with a junction-type body contact forsuppression of pass gate leakage

A SOI MOSFET structure with a junction-type body contact [body-junctioned-to-gate (BJG)] is proposed to effectively suppress the parasitic bipolar effect in all kinds of MOSFETs including the pass transistor, which can be realized with compact design and simple processes. It utilizes the buried contact process to minimize the area consumption. Various on-chip test circuits have been fabricated to verify the BJG characteristics and it is shown that the proposed structure provides nearly perfect immunity against the circuit failure caused by the parasitic bipolar effect and an excellent speed performance, so that it can be a promising candidate for the SOI circuits     

横向SOI锗硅光电探测器的数值模拟

采用Atlas对SOI/CMOS兼容横向pin近红外锗硅光探测器进行了模拟分析。结果显示,外延应变SiGe层产生禁带变窄,形成了横向的二维空穴势阱沟道。在3V反向偏压下,电场沿横向均匀分布,光吸收层基本完全耗尽,光生载流子得到有效收集;与Si的光电响应相比,出现较明显的响应波长范围向长波长方向扩展、响应峰值波长向长波长方向移动,证实了探测器结构的有效性和其良好的光电性能。     

Design of 50-nm vertical MOSFET incorporating a dielectric pocket

A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography.     

斜埋氧SOI LDMOS高压器件新结构

为了提高基于绝缘体上的硅(SOI)技术实现的横向扩散金属氧化物半导体器件(SOI LDMOS)的击穿电压,提出了斜埋氧SOI LDMOS(S SOI LDMOS)耐压新结构。当器件关断时,倾斜的埋氧层束缚了大量的空穴,在埋氧层上界面引入了高密度的正电荷,大大增强了埋氧层中的电场,从而提高了纵向耐压。另外,埋氧层的倾斜使器件漂移区厚度从源到漏线性增加,这就等效于漂移区采用了线性变掺杂,通过优化埋氧层倾斜度,可获得一个理想的表面电场分布,提高了器件的横向耐压。对器件耐压机理进行了理论分析与数值仿真,结果表明新结构在埋氧层厚度为1μm、漂移区长度为40μm时,即可获得600 V以上的击穿电压,其耐压比常规结构提高了3倍多。     

Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

Semiconductors - In this work, drain current ID for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET...     

The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs

The thickness effects of a high-tensile-stress contact etch stop layer (HS CESL) and the impact of layout geometry (length of diffusion (LOD) and gate width) on the mobility enhancement of lang100rang/(100) 90-nm silicon-on-insulator (SOI) n-channel MOSFETs (nMOSFETs) were studied in detail. Additionally, the low-frequency characteristics were inspected using low-frequency noise investigation for floating body (FB)-SOI nMOSFETs. Experimental results show that a device with a 1100-Aring HS CESL has worse characteristics and hot-carrier-induced degradations than a device with a 700-Aring; HS CESL due to larger stress-induced defects. The lower plateau of the Lorentzian noise spectrum that was observed from the input-referred voltage noise S_vg implies a higher leakage current for devices with a 1100-Aring HS CESL. On the other hand, it was found that devices with narrow gate widths have higher driving capacity for a larger fringing electric field and higher compressive stress in the direction perpendicular to the channel. Because of the more serious impact of compressive stress in a direction parallel to the channel, a device with shorter LOD experiences more serious performance degradation