Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.     

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.This research was supported by the National Science Foundation under grant MIP-9222481.     

模拟电路模块级软故障特征的提取与故障诊断

介绍了一种模拟电路故障诊断中功能模块级的单模块软故障模型的建立理论和特征提取的方法,运用该方法提取的单模块故障特征不仅可以有效区分单模块电路中的各类故障,而且单模块电路的故障特征还可以在多模块电路的单故障和多故障的情况下应用。仿真结果表明,通过采样电路输出并进行相应的信号处理来提取故障模型,可以准确地定位多模块故障电路的故障部位。     

基于故障映射的并行故障仿真方法

提出了基于故障映射的4值并行故障仿真方法.这一方法首先把电路划分成无扇出区域和扇出茎区域,然后将非扇出茎故障映射为扇出茎故障,减少了需要显式并行仿真的故障数目,提高了仿真器的性能.实验结果验证了文中方法的有效性.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

基于分数阶相关的模拟集成电路软故障诊断* Deng Yong(邓勇), Shi Yibing(师奕兵)and Zhang Wei(张伟)

针对模拟集成电路软故障诊断的难题,提出了基于分数阶相关的方法。首先,利用分数阶小波包将待测试电路(CUT)的Volterra级数进行分解,计算出分数阶相关函数。然后,用得到的分数阶相关函数构造出待测试电路的故障特征。通过对故障特征的比较,可以将待测试电路的各种软故障状态进行辨识并对故障实现定位。标准电路的仿真实验描述了这一方法并验证了该方法对模拟集成电路软故障诊断的有效性。     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

一种基于神经网络的模拟电路故障诊断方法

模拟电路故障诊断一直是一项富有挑战性的研究课题。文章在简要介绍BP神经网络基本原理的基础上,以差分放大电路为例,设计并实现了基于BP算法的模拟电路故障诊断方法,建立了模拟电路故障诊断BP神经网络模型。实验表明,该模型的辨识精度高,能实现对模拟电路故障的正确诊断。     

模拟电路故障诊断的PSpice与Matlab仿真分析研究

根据模拟电路故障诊断中的测前模拟诊断SBT法,本文采用PSpice对待测电路CUT故障进行模拟仿真,通过小波包分析和信息熵方法提取故障电路输出信号的特征向量,利用Matlab设计的神经网络算法构建故障分类器并对电路故障进行识别与诊断。仿真实验结果表明将PSpice与Matlab相结合的诊断方法能够有效地诊断模拟电路故障,为模拟电路故障诊断的教学和科研提供参考。     

基于小波分析和人工免疫算法的模拟电路故障诊断

受生物免疫系统自己-非己识别过程的启发,提出了一种基于小波分析和人工免疫算法的模拟电路故障诊断的新方法。该方法首先利用小波变换,归一化和主元分析法作为预处理提取模拟电路的最优故障特征向量,然后利用反面选择算法的检测器对故障信息进行检测,从而实现模拟电路故障的分类。计算机仿真证明该方法是可行的。     

基于遗传算法的容差模拟电路故障诊断

给出了用于模拟电路元件参数识别的多频传递函数法的过程,并对故障诊断方程的可解度进行了分析,在此基础上,将诊断方程的求解转化为非线性函数的优化问题,并运用改进的遗传算法来解决这个问题,算法实例表明该方法简化了故障诊断方程的求解过程,加速了容差电路故障元件的定位,有一定的应用价值。     

基于ELM网络的模拟电路故障诊断

由于模拟电路的非线性、易受外界干扰等因素,模拟电路的故障在设备总故障中占很大的比例。因此,对模拟电路的故障诊断技术进行深入研究具有很重要的意义。文中针对雷达电路的故障进行快速有效的特征提取,采用神经网络中ELM网络建立诊断系统结构,并通过对具体电路的仿真,输出ELM网络的诊断结果。实际应用表明,该系统具有操作简便、诊断精度高的特点,达到了设计要求。     

基于闭环集成运放的模拟电路模块级软故障诊断

基于斜率故障模型,提出了一种诊断模拟电路中基于闭环集成运算放大器的模块级软故障的字典法.在由闭环运放组成的模拟电路中,通过对电路以闭环运放及与其输入直接相连的元件看作一个整体划分模块,对各个模块中的任一元件或进行宏模型替代之后的运放等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现电路中相应模块包含的运放和所有元件的软故障诊断.给出了运放的等效宏模型和模块级软故障的诊断步骤,并用仿真实例证明了该诊断方法的有效性.     

基于神经网络与证据理论的模拟电路故障诊断

论述了利用多类电量测试信息、应用神经网络与D-S证据理论实现模拟电路故障诊断的基本原理,提出了一种基于可测点电压与不同测试频率下的电路增益经决策层信息融合的故障诊断新方法.分别利用此两类测试信息,各用一个独立的改进BP网络对电路进行初步诊断,再运用所提融合诊断算法实现故障定位.模拟实验结果表明:所提方法对硬故障与元件参数偏移较小的软故障均适用,故障定位准确率高.     

Dynamic effects in the detection of bridging faults in CMOS ICs

Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors < T ₀, T ₁ >, in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T₀ initializes the faulty signal to a logic value different from the fault-free one produced by T ₁. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.     

模拟VLSI电路故障诊断的相关分析法

为了提高模拟VLSI电路的测试精度,提出了一种基于数字信号处理的模拟VLSI电路测试方法，将测试响应经余弦调制实现的数字滤波器组完成子带滤波,随后对各子带滤波序列进行能量计算和相关分析,实现模拟响应的数字特征提取，对国际标准电路中的19个故障的实验表明：子带滤波序列的能量计算适合诊断硬故障； 相关分析既可诊断硬故障,又可诊断软故障，实验还表明该方法对故障的分辨率远高于文献[7]。     

一种基于小波-神经网络的模拟电路故障诊断方法

小波分析具有数据压缩和特征提取的特性,神经网络具有非线性映射和学习推理的优点。结合两者的特点,提出了一种基于小波与神经网络的模拟电路故障诊断方法,该方法用小波变换对电路响应信号进行特征提取,从而简化神经网络的结构,降低计算的复杂度,加快了训练速度。对实例仿真表明,该法能有效地对模拟电路进行故障诊断。