AlGaN/GaN HEMT With a Transparent Gate Electrode

AlGaN/GaN high-electron-mobility transistors (HEMTs) with indium tin oxide (ITO) transparent gate electrodes have been fabricated. The transparent gate electrodes enable the investigation of photon, electron, and phonon behaviors in active regions in HEMTs using optical characterizations such as electroluminescence, photoluminescence, and Raman spectroscopy technologies. Leakage current, on/off ratio, and transparency have been compared for transistors using Ni/Au/Ni, ITO, and Ni/ITO stacks as gate electrodes. Compared to the Ni/Au/Ni gate transistor, the ITO gate device shows a comparable current gain cutoff frequency (f _T) but a much lower power gain cutoff frequency (f _max) due to the low conductivity of ITO.     

A Novel Analysis of a $Ku$-Band Planar p-i-n Diode Limiter

Two new analyses for a single-stage limiter were presented; one is an analytic approach based on the approximation of the voltage waveforms of a p-i-n diode in the limiter, while the other models the p-i-n diode by a p-n diode. The analytic expressions resulting from the analytic approach explicitly show the role of the diode parameters on the limiter performances, which can be used as a guide to select adequate p-i-n diodes for the limiter. The two analyses were verified using the large-signal p-i-n diode model developed by measurements. Our analysis was then extended to multistage limiters. Based on our analysis, we designed and fabricated a limiter with an insertion loss of 1.3 dB and a flat leakage of 11.7 dBm for a $Ku$-band input power of 20 W.      

Subthreshold Parallel FM-to-Digital $Delta$– $Sigma$ Converter With Output-Bit-Stream Addition by Interleaving

Single and parallel subthreshold frequency-modulation-to-digital $Delta$–$Sigma$ modulators (FDSMs) have been implemented in a standard 90-nm CMOS technology. Theoretical and measured results are presented for both topologies. The 512-stage parallel FDSM adopts a tunable delay line and achieves bit-stream addition by interleaving at the output stage. This architecture, with respect to the conventional parallel FDSM, reduces power, area, and complexity at the cost of using clocks with higher speed in its output stage. In addition, compared to the single FDSM, the parallel converter shows an improvement in signal-to-quantization-noise ratio of more than 25 dB at supply voltages as low as 300 mV.      

Silicon Resonator Based 3.2 $mu$W Real Time Clock With $pm$10 ppm Frequency Accuracy

This paper presents an ultra-low power generic compensation scheme that is used to implement a real time clock based on an AlN-driven 1 MHz uncompensated silicon resonator achieving 3.2 ?W power dissipation at 1 V and ±10 ppm frequency accuracy over a 0-50°C temperature range. It relies on the combination of fractional division and frequency interpolation for coarse and fine tuning respectively. By proper calibration and application of temperature dependent corrections, any frequency below that of the uncompensated resonator can be generated yielding programmability, resonator fabrication tolerances and temperature drift compensation without requiring a PLL. To minimize the IC area, a dual oscillator temperature measurement concept based on a ring oscillator/resistor thermal sensor was implemented yielding a resolution of 0.04°C. The IC was fabricated on a 0.18 ?m 1P6M CMOS technology.     

A Geometric Process $delta$-Shock Maintenance Model

A geometric process $delta$ -shock maintenance model for a repairable system is introduced. If there exists no shock, the successive operating time of the system after repair will form a geometric process. Assume that the shocks will arrive according to a Poisson process. When the interarrival time of two successive shocks is smaller than a specified threshold, the system fails, and the latter shock is called a deadly shock. The successive threshold values are monotone geometric. The system will fail at the end of its operating time, or the arrival of a deadly shock, whichever occurs first. The consecutive repair time after failure will constitute a geometric process. A replacement policy $N$ is adopted by which the system will be replaced by a new, identical one at the time following the $N$th failure. Then, for the deteriorating system, and the improving system, an optimal policy $N^{ast}$ for minimizing the long-run average cost per unit time is determined analytically.      

Analysis, Design, and $X$-Band Implementation of a Self-Biased Active Feedback $G_{m}$ -Boosted Common-Gate CMOS LNA

This paper explores the use of active feedback to boost the transconductance of a common-gate (CG) low-noise amplifier and achieve simultaneous low noise and input power match. Unlike transformer coupled topologies, the CG input stage is dc-coupled to a self-biased common-source feedback amplifier (for $g_{m}$ boosting), thus eliminating the need of external bias circuitry. Noise and intermodulation analysis with and without $g_{m}$ boosting are extensively studied yielding closed-form expressions of the noise figure (NF) and third-order input-referred intercept point (IIP3) that are useful for circuit design and optimization. A 9.6-GHz differential prototype implemented in a 0.18-$mu$ m technology using only NMOS transistors, achieves a minimum NF of 4 dB, an IIP3 of ${-}$ 11.3 dBm, a return loss of ${-}$ 17 dB, and a transducer gain of 18 dB while dissipating 10 m (excluding buffer circuit) from a 1.8-V supply voltage. The active chip area is 0.11 $mu$m $^{2}$.      

A Fully Differential Comparator-Based Switched-Capacitor $DeltaSigma$ Modulator

In this brief, a fully differential comparator-based switched-capacitor (CBSC) second-order delta-sigma $(DeltaSigma)$ modulator is presented. To ensure differential operation, the CBSC $DeltaSigma$ modulator utilizes a common-mode feedback circuit to balance the pull-up current and the pull-down current in the ramp generator. This modulator has been fabricated in a standard 0.18-$muhbox{m}$ CMOS process. The active area is 0.21 $hbox{mm}^{2}$, and the power consumption, excluding output buffers, is 0.42 mW from a 1.8-V supply. This modulator achieves 65.3-dB signal-to-noise-plus-distortion ratio and an input dynamic range of 71 dB when sampled at 2.56 MS/s $(hbox{OSR} = 64)$.      

The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.      

$C$ -Band Optical 90$^{circ}$ -Hybrids Based on Silicon-on-Insulator 4 $times$ 4 Waveguide Couplers

We demonstrate 4times4 multimode interference couplers in a silicon-on-insulator rib waveguide technology that enable compact integrated fully passive optical 90deg-hybrid devices with operation across the C-band.     

Ring Oscillator Technique for MOSFET $CV$ Characterization

A technique for extracting small signal MOSFET gate capacitance as a function of bias voltage from measurements of circuit delay and power is described. This approach makes use of a ring oscillator with stages in which an independent bias voltage is applied to the gates of MOSFETs driven by an inverter. The square wave signal circulating around the ring oscillator, at a reduced power supply voltage, serves as a small signal excitation for the $CV$ characterization. Gate charging times of order 40 ps enable capacitance measurement in the presence of the high parallel conductance of thin gate dielectrics. MOSFET parameters such as inversion and depletion capacitances and electrical channel length can be self-consistently compared with circuit power/performance, all derived as averages over hundreds of MOSFETs from the same test structure. This minimizes dependencies on layout, spatial and statistical variations, as well as other ambiguities that can exist when a variety of test structures is used to evaluate different MOSFET and circuit performance parameters. At $≪$1 MHz, the frequency divided output is compatible with standard in-line test. Data from experimental partially depleted silicon-on-insulator hardware at the 65-nm CMOS technology node are presented.      

Optimization of Passively Repetitively $Q$-Switched Three-Level Lasers

A generalized model of a passively repetitively $Q$-switched three-level laser is presented. The method for evaluation of the small-signal gain coefficient and the dissipative losses of a three-level laser is shown. To demonstrate the use of this optimization procedure, it was applied to a microchip laser generating 1.5- $mu$m radiation. The model may be expanded for a four-level laser by replacing the calculation of the small-signal gain coefficient.      

12 GHz $F_{rm MAX}$ GaN/AlN/AlGaN Nanowire MISFET

GaN/AlN/AlGaN/GaN nanowire metal–insulator–semiconductor field-effect transistors (MISFETs) have been fabricated for the first time with submicrometer gate lengths. Their microwave performances were investigated. An intrinsic current-gain cutoff frequency $(F_{T})$ of 5 GHz as well as an intrinsic maximum available gain $(F_{rm MAX})$ cutoff frequency of 12 GHz have been obtained for the first time and associated with a gate length of 0.5 $muhbox{m}$. These results show the great potentiality of GaN-based nanowire FETs for microwave applications.      

Parallel Continuous-Time $DeltaSigma$ ADC for OFDM UWB Receivers

A parallel multibit continuous-time (CT) $DeltaSigma$ analog-to-digital converter for an orthogonal-frequency-division-multiplexing (OFDM) ultrawideband receiver intended to operate according to the IEEE 802.15.3a or the ECMA 368 (ISO/IEC 26907) standards has been designed. The overall CT $DeltaSigma$ converter consists of two modulators covering two unequal subbands (low-pass (LP) and bandpass (BP) subbands) that are arranged to operate in parallel and whose respective noise transfer functions (NTFs) are designed to match its corresponding frequency band. The composite NTF for the overall converter is defined as the minimum gain value out of these two individual NTFs. The LP and BP subbands were designed by using third- and fourth-order modulators, respectively, based on a 3-bit quantizer and operating at a clock frequency of 1056 MHz. NTF zero locations were optimized according to the criterion that all the in-band composite NTF gain maxima have approximately the same value. Combining OFDM signal characteristics and converter parameters, the effect of the quantization noise on the overall converter performance has been analytically derived. A simulation program has been realized to verify the performance of the converter.      

$f_{T}$ and $f_{rm MAX}$ of 47 and 81 GHz , Respectively, on N-Polar GaN/AlN MIS-HEMT

In this letter, we demonstrate the record small-signal performance from N-polar GaN-based metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using a GaN spacer structure with an AlN barrier to reduce alloy scattering. High Si doping in GaN without excessive surface roughening has been achieved using a digital doping scheme. A low ohmic contact resistance of 0.16 $Omega cdot hbox{mm}$ was measured. Submicrometer gates were fabricated by electron-beam lithography using a triple-layer resist process. $f_{T}$ and $f_{rm MAX}$ of 47 and 81 GHz, respectively, were obtained for the 150-nm-gate-length device. Further analysis has been done to understand the effect of access resistance on the high-frequency performance, defining a pathway for getting a higher gain and thus achieving a better high-frequency performance from N-polar GaN-based HEMTs.      

New Completely Regular $q$-ary Codes Based on Kronecker Products

For any integer ? ? 1 and for any prime power q , an explicit construction of an infinite family of completely regular (and completely transitive) q-ary codes with d = 3 and with covering radius ? is given. The intersection array is also computed. Under the same conditions, the explicit construction of an infinite family of q-ary uniformly packed codes (in the wide sense) with covering radius ?, which are not completely regular, is also given. In both constructions, the Kronecker product is the basic tool that has been used.     

Linear Size Optimal $q$-ary Constant-Weight Codes and Constant-Composition Codes

An optimal constant-composition or constant-weight code of weight w has linear size if and only if its distance d is at least 2w-1. When d ? 2w, the determination of the exact size of such a constant-composition or constant-weight code is trivial, but the case of d=2w-1 has been solved previously only for binary and ternary constant-composition and constant-weight codes, and for some sporadic instances. This paper provides a construction for quasicyclic optimal constant-composition and constant-weight codes of weight w and distance 2w-1 based on a new generalization of difference triangle sets. As a result, the sizes of optimal constant-composition codes and optimal constant-weight codes of weight w and distance 2w-1 are determined for all such codes of sufficiently large lengths. This solves an open problem of Etzion. The sizes of optimal constant-composition codes of weight w and distance 2w-1 are also determined for all w ? 6, except in two cases.     

Broadband Lumped-Element Integrated $N$-Way Power Dividers for Voltage Standards

This paper presents a monolithically integrated broadband lumped-element Wilkinson power divider centered at 20 GHz, which was designed and fabricated to uniformly distribute power to arrays of Josephson junctions (JJs) for superconducting voltage standards. This solution achieves a fourfold decrease in chip area, and a twofold increase in bandwidth (BW) when compared to the previous narrowband distributed circuit. A single Wilkinson divider demonstrates 0.4-dB maximum insertion loss (IL), a 10-dB match BW of 10–24.5 GHz, and a 10-dB isolation BW of 13–30 GHz. A 16-way four-level binary Wilkinson power divider network is characterized in a divider/attenuator/combiner back-to-back measurement configuration with a 10-dB match BW of 10–25 GHz. In the 15–22-GHz band of interest, the maximum IL for the 16-way divider network is 0.5 dB, with an average of 0.2 dB. The amplitude balance of the divider at 15, 19, and 22 GHz is measured to be ${pm}{hbox{1.0 dB}}$ utilizing 16 arrays of 15 600 JJs as on-chip power detectors.      

Simplifying the Design of $SigmaDelta$ Modulators Using FGMOS Transistors

This paper presents the novel design of a second-order continuous-time low-power and low-voltage $SigmaDelta$ modulator. The modulator illustrates a design philosophy based on taking advantage of the extended number of degrees of freedom of the floating-gate MOS transistor. The transistor is simultaneously used to fulfill the following: simplify the topology; accurately implement the modulator coefficients; compensate for gain losses in the integrator and several nonidealities in the comparator; increase the signal range; reduce distortion; shift signal levels according to the specific requirements of individual devices; implement an easy common-mode sensing and feedback strategy; and tune the loop filter and reset the comparator. The modulator operates at 1 V and consumes just over 5 $muhbox{W}$ of power for a signal-to-noise-and-distortion ratio of 60 dB and a maximum bandwidth of 2 kHz, which are typical of many biomedical applications.      

Design of Exactly Linear Phase $K$-Regular IIR Half-Band Filter

This paper proposes a novel method to design exactly linear phase infinite impulse response half-band filters with arbitrary regularity. Broadly speaking, the design problem is formulated as a semi-infinite program, which is then turned into a semidefinite program of minimal order via a new linear matrix inequality characterization of convex hulls of trigonometric polynomials. In contrast to maximally flat approach, the proposed method allows direct control of various design parameters, which in turn enables the synthesis of filters with better transition response. The viability of the proposed method is demonstrated through several numerical examples.      

Theoretical Model of Yb $^{3 + }$-Er $^{3 + }$-Tm $^{3 + }$-Codoped System for White Light Generation

We present a theoretical model of Yb$^{3 + }$-Er $^{3 + }$-Tm $^{3 + }$-co-doped system for white light generation. The energy level, electron transition process and numerical model are proposed to calculate fluorescence intensity of the system pumped by 980 nm laser. The numerical results reveal that our theoretical model is in good agreement with experimental results in literature. Optimal active ion concentrations are proposed to enable the system to emit red, blue and green lights which are mixed to generate white light in telluride matrix for display and lighting system.