Substitution of Paraelectric for Conventional Dielectric in AlGaN/GaN MISFETs

A ferroelectric material of paraelectric state is proposed as a substitute for the conventional dielectric in AlGaN/GaN metal–insulator–semiconductor field-effect transistors (MISFETs). Owing to its switchable polarization, the maximum transconductance of a barium strontium titanate (BST)/AlGaN/GaN metal–paraelectric–semiconductor FET (MPSFET) is significantly improved by 44% as compared to a conventional SiN/AlGaN/GaN MISFET. The pinchoff voltage is greatly reduced from $-!$10.7 V for the MISFET to $-$4.7 V for the MPSFET, accompanied with a distinct improvement in the pinchoff characteristics and suppression of soft pinchoff. Small-signal measurements result a comparable frequency performance of the FETs with BST and SiN gate dielectrics. Based on a self-consistent calculation, the switchable polar nature of the paraelectric is revealed to be essential for improving the device transconductance.      

A novel depletion-gate amorphous silicon thin-film transistor

A novel type of amorphous silicon (a-Si) thin-film transistor (TFT) in which a depletion gate is added to the top of the second nitride layer of a conventional a-Si TFT has been fabricated. In this transistor, switching is done by the depletion gate instead of the accumulation gate as in conventional a-Si TFTs. The pinch-off voltage and ON-OFF current ratio of the transistor can be changed by the accumulation gate bias. The transistor exhibits high ON-OFF current ratio, low contact resistance, and low gate-source capacitance     

Analysis of High-Speed GaAs Source-Coupled FET Logic Circuits

A source-coupled FET logic (SCFL) circuit is proposed for gigabit rate digital signaf processing. FET threshold voltage tolerance in the SCFL circuit and the SCFL circnit performance are presented. The speed of the SCFL gate depends on the operating region of the FET. For high-speed operation, FET's drain-to-source voltage fdgher than a pinchoff voltage has to be suppfied. The SCFL gate, which is composed of 1.5-pm gate-length FET's, showsthat the minimum propagation time is predicted to be 25 ps/gate. Mhimum rise time and fall time are expected to be S4 ps and 51 ps, respectively. Maximum RZ data rate is expected to be 5.6 Gb/s. The SCFL circnit is applicablefor high-speed dlgitaf sigmd processing.     

An ion-implanted Schottky-barrier gate field-effect transistor

Techniques of fabricating an n-channel silicon field-effect transistor using phosphorus ion implantation and a platinum silicide Schottky-barrier gate (SB-FET) have been developed. The platinum silicide Schottky-barrier top gate is part of the contact metallization process. The phosphorus-doped channel is obtained by using a 50-keV ion-implanted predeposition and an 1100°C drive-in. A range of implantation doses and drive-in times were used to achieve various SB-FET characteristics. A threshold/pinchoff voltage range of +0.4 to -7.5 V has been obtained with typical spreads of approximately 0.1 V across the slice. A positive threshold voltage represents a SB-FET that is normally off and is turned on by a forward-biased gate. Results have been obtained for     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

New split FET technique for measurements of source seriesresistance applied to amorphous silicon thin film transistors

A split field-effect transistor (SFET) is proposed for measuring source and drain series resistances. This device is made by splitting a conventional thin-film transistor (TFT) from the source to the drain in such a way that the gate width of each half is a linear function of the distance from the source. The analysis shows that the intrinsic current-voltage characteristics of such a device should be symmetrical with respect to the polarity of the drain-to-source voltage. Hence, the observed asymmetry of the device characteristic yields direct information about the differences between source and drain series resistances, which are inversely proportional to the contact width. For an a-Si TFT it is shown that the source series resistance is proportional to the inverse square root of the drain current in a wide range of currents. The technique can be applied to a large variety of FETs. For a-Si TFTs, it provides an accurate tool for determining the effects of contact overlap, bias stress, and temperature dependences of series resistances     

Experimental comparisons in the electrical performance of long and ultrashort gate length GaAs MESFET's

Electrical properties of GaAs single-gate and dual-gate MESFET's with gate lengths of 1.2 µm and 0.2 µm have been compared. By reducing the gate length to 0.2 µm, a very high zero-gate-bias drain current Idssand a large increase in the pinchoff voltage were observed in both single-gate and dual-gate devices, Idssin the shorter gate FET was found to be very close to the full channel current. Only a slight improvement in the maximum intrinsic gmwas noted in the 0.2 µm FET's. The knee voltage for the zero-gate-bias curve was larger in the shorter gate FET. At low current levels, soft pinchoff and soft saturation behaviors were observed in the very short gate FET's. A striking feature of the GaAs MESFET is that its output conductance at large drain voltages does not degrade with shorter gate lengths.     

Theoretical analysis of HEMT breakdown dependence on device designparameters

A two-dimensional numerical analysis is presented to investigate the breakdown characteristics of single- and double-channel AlGaAs/GaAs HEMTs. The influence of the doped layer thickness and the thickness of an undoped i-layer under the gate is analyzed. Impact ionization is considered to be the dominant breakdown mechanism. All simulations reveal the existence of a high electric field region near the gate contact. Breakdown occurs in the gate-drain region and the (breakdown) path which maximizes the ionization integral is entirely in the AlGaAs layer. For increased donor layer thickness, single-channel devices biased near pinchoff have gate-drain breakdown voltages varying from 8 to 14 V with corresponding peak electric field values in the range of 8.2×10⁵ to 2.4×10⁶ V/cm. The breakdown voltage increases with increasing gate bias |V _gs| due to a screening effect of transverse from longitudinal electric field. Double-channel HEMTs have slightly higher breakdown than single-channel, especially near pinchoff and for thin donor layers     

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive V_TH shift within 0.4 V and negative V_TH shift within-1.2 V and it is robust and promising for high-resolution display.     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Microwave performance of AlGaN/GaN metal insulator semiconductorfield effect transistors on sapphire substrates

Metal-insulator-semiconductor field effect transistors (MISFETs) from surface-passivated undoped AlGaN/GaN heterostructures on sapphire were fabricated. Measured static output characteristics includes full channel currents (I_dss) of roughly 750 mA/mm with gate-source pinchoff voltages of -10 V and peak extrinsic transconductancies (g_m) of 100-110 mS/mm. Increased surface roughness resulting from a gate recess process to reduce the pinchoff voltage introduces gate leakage currents in the micro-amps regime. With evidence for reduced dc-to-rf dispersion from pulsed gate transfer characteristics, these devices at 4 GHz with 28.0 V bias generated maximum output power densities of 4.2 W/mm with 14.5 dB of gain and 36% power added efficiency     

TiA1和TiPtAu栅GaAs MESFET稳定性研究

在高温和大栅电流下 ,对 Ti Al栅和 Ti Pt Au栅 MESFET的稳定性进行了比较研究 ,结果表明 :( 1)两种器件的击穿电压稳定 ,栅 Schottky接触二极管理想因子 n变化不明显 ;( 2 ) Ti Al栅的 MESFET的栅特性参数 (栅电阻 Rg,势垒高度 Φb)变化明显 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 等 )保持相对不变 ;( 3)对 Ti Pt Au栅MESFET来说 ,栅 Schottky二极管特性 (栅电阻 Rg,势垒高度 Φb)保持相对稳定 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 、跨导 gm 等 )明显变化 ,适当退火后 ,有稳定的趋势。这两种器件的参数变化形成了鲜明的对比。     

A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (⩽600°C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity     

铁电栅材料GaN基场效应晶体管的特性

针对铁电薄膜/GaN基FET结构,利用数值方法研究了铁电栅材料自发极化强度PS变化对GaN基表面电子浓度nS和场效应晶体管转移特性Id-Vg的影响,给出了典型PS和εr值下跨导gm与Vg的关系。结果表明:零栅压下,nS在随PS(0～±59μC/cm2)变化时有4～6个数量级的提高或降低;当Vg=0.65V、PS为-26～26μC/cm2时,nS提高约4个数量级;负栅压下,nS因受引起电子耗尽的PS的影响而降低6～7个数量级,而PS未对Id-Vg产生明显影响,跨导gm在1V左右的栅偏压下达到最大值。这些结果对利用铁电极化和退极化可能改善新型器件性能的研究具有重要意义。     

High-voltage TFT fabricated in recrystallized polycrystallinesilicon

High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 μm. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage     

On the possible effects of AlGaAsSb growth parameters on the 2-DEGconcentration in AlGaAsSb/InGaAs/AlGaAsSb QW's

The absence of pinchoff in the room temperature current-voltage characteristics of certain AlGaAsSb/InGaAs/AlGaAsSb-based high electron mobility transistors (HEMT's) is investigated by theoretical calculations. The room temperature pinchoff properties are strongly affected by the Al mole fraction in the buffer layer, the In mole fraction in the channel, the unintentional acceptor doping level of the lattice-matched quaternary buffer, and the quantum well width. The use of InAs as the channel material imposes strict conditions on the composition and the unintentional acceptor doping of the buffer layer. With decreasing In mole fraction, the restriction is relaxed. A higher Al mole fraction in the buffer, along with a lower In mole fraction in the channel, results in superior pinchoff characteristic and lower gate leakage     

高可靠性Cu BCE a-IGZO TFTs的制作

背沟道刻蚀型（BCE）非晶氧化铟镓锌薄膜晶体管（a-IGZO TFT）具有工艺简单、寄生电容小以及开口率高等优点,但BCE IGZO器件背沟道易受酸液和等离子体损伤,进而引起TFT均匀性和稳定性等方面问题,随着GOA技术的导入,对TFT器件电学性能的均匀性和稳定性提升的要求也日益迫切,因此开发高信赖性BCE IGZO TFT是技术和市场的迫切要求。本文主要分析了基于IGZO的背沟道刻蚀型薄膜晶体管电学性质,通过优化钝化层材料,色阻材料以及GOA TFT结构等削弱因背沟道水汽吸附引起的器件劣化,偏压温度应力测试结果显示优化后的TFT展现了良好的稳定性——在80℃,栅极30 V负向偏压条件下,2 000 s的ΔV_th小于1 V。最终,利用优化的IGZO TFT制作了215.9 mm（85 in）8K4K 120 Hz液晶显示器。     

Ferroelectric neuron integrated circuits using SrBi2Ta2O9-gate FET's and CMOS Schmitt-triggeroscillators

A pulse frequency modulation (PFM) type ferroelectric neuron circuit composed of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) and a CMOS Schmitt-trigger oscillator was fabricated on an SOI structure, in which SrBi₂Ta₂O₉ (SBT) was used as a ferroelectric gate material of the FET. It was found that the fabricated MFSFET showed a relatively good I_D-V_G (drain current versus gate voltage) characteristic with a hysteresis loop due to the ferroelectricity of the SBT film and that it acted as a synapse device with adaptive-learning function. It was also found that the output pulse height of the circuit was as high as the power supply voltage and that output pulse frequency was changed as the number of applied input pulses increased