In-pixel autoexposure CMOS APS

A CMOS active pixel sensor (APS) with in-pixel autoexposure and a wide dynamic-range linear output is described. The chip features a unique architecture enabling a customized number of additional bits per pixel per readout, with minimal effect on the sensor spatial or temporal resolution. By utilizing multiple readouts via real-time feedback, each pixel in the field of view can automatically set an independent exposure time, according to its illumination. A customized, large increase in the dynamic range can be achieved and a scene containing both bright and dark regions can be captured. A prototype of 64 /spl times/ 64 pixels has been fabricated using 1-poly 3-metal CMOS 0.5 /spl mu/m n-well process available through MOSIS. Power dissipation is 3.7 mW at V/sub DD/ = 5 V. The special functions have been verified experimentally, and an increase of 2 bits over the inherent dynamic range captured is shown.     

A DPS array with programmable resolution and reconfigurable conversion time

A CMOS digital pixel sensor (DPS) with programmable resolution and reconfigurable conversion time is described. The chip features a unique architecture based on the pulse width modulation (PWM) technique and operates with either an 8-b or 4-b accuracy. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a shorter conversion time and a two times increase in spatial resolution. Two quantization schemes are studied, namely, the uniform and the nonuniform time-domain quantizers, which are referred to as UQ and NUQ, respectively. It is shown that the latter scheme not only permits to linearize the nonlinear response of the PWM sensor, but also allows to significantly speed up the conversion time, particularly for wide dynamic range and low coding resolutions. A prototype of 32/spl times/32/64/spl times/32 pixels has been fabricated using 1-poly, 5-metal CMOS 0.35-/spl mu/m n-well standard process. Power dissipation is 10 mW at V/sub DD/=3.3 V, dynamic range is 90 dB, while dark current was measured at 1 pA. The reconfiguration features of the chip have been verified experimentally.     

A high fill factor and progressive scan PtSi Schottky-barrier IR-CCD image sensor using new wiring technology

A back surface illuminated 130/spl times/130 pixel PtSi Schottky-barrier (SB) IR-CCD image sensor has been developed by using new wiring technology, referred to as CLOSE Wiring, CLOSE Wiring, designed to effectively utilize the space over the SB photodiodes, brings about flexibility in clock line designing, high fill factor, and large charge handling capability in a vertical CCD (VCCD). This image sensor uses a progressive scanned interline-scheme, and has a 64.4% fill factor in a 30 /spl mu/m/spl times/30 /spl mu/m pixel, a 3.9 mm/spl times/3.9 mm image area, and a 5.5 mm/spl times/5.5 mm chip size. The charge handling capability for the 3.3 /spl mu/m wide VCCD achieves 9.8/spl times/10/sup 5/ electrons, The noise equivalent temperature difference obtained was 0.099 K for operation at 120 frames/sec with a 50 mm f/1.3 lens.<>     

Low-power InP-HEMT switch ICs integrating miniaturized 2/spl times/2 switches for 10-Gb/s systems

This paper presents a wideband cold-FET switch with virtually zero power dissipation. The use of InP HEMTs with a low R/sub on//spl middot/C/sub off/ product enables us to configure a DC-to-over-10-GHz single-pole double-throw (SPDT) switch without using a shunt FET. The series-FET configuration offers a logic-level-independent interface and makes possible positive control voltage operation in spite of using depletion-mode FETs. A miniaturized 2/spl times/2 switch using two SPDT switches yields an insertion loss of less than 1.16 dB and isolation of more than 21.2 dB below 10 GHz, which allows us to increase the scale of the switch in a single chip easily. The add-drop operation combining two 2/spl times/2 switches in a single chip and a 4/spl times/4 switch IC integrating four 2/spl times/2 switches are presented. The packaged ICs achieve error-free operation up to 12.5 Gb/s with either positive or negative logic-level input. Extremely fast switching of /spl sim/140 ps is also successfully demonstrated.     

30-GHz-band over 5-W power performance of short-channel AlGaN/GaN heterojunction FETs

This paper describes the small-signal characterization through delay-time analysis and high-power operation of the Ka-band of AlGaN/GaN heterojunction field-effect transistors (FETs). An FET with a gatewidth of 100 /spl mu/m and a gate length of 0.09 /spl mu/m has exhibited a current gain cutoff frequency (f/sub T/) of 81 GHz, a maximum frequency of oscillation (fmax) of 187 GHz, and a maximum stable gain of 10.5 dB at 30 GHz (8.3 dB at 60 GHz). Delay-time analysis has demonstrated channel electron velocities of 1.50/spl times/10/sup 7/ to 1.75/spl times/10/sup 7/ cm/s in a gate-length range of 0.09-0.25 /spl mu/m. State-of-the-art performance-saturated power of 5.8 W with a linear gain of 9.2 dB and a power-added efficiency of 43.2%-has been achieved at 30 GHz using a single chip having a gatewidth of 1.0 mm and a gate length of 0.25 /spl mu/m.     

A novel bidirectional CMOS transceiver for chip-to-chip optical interconnects

A novel bidirectional complementary metal-oxide-semiconductor (CMOS) transceiver for chip-to-chip optical interconnects operating at 2.5 Gb/s is proposed, which shares the common block of a receiver and a transmitter on a single chip. The share of the common block of two circuits makes it possible to save 55% or 20% of power dissipation, depending on the operating mode. The chip in 0.18-/spl mu/m CMOS technology occupies an area of 0.82/spl times/0.82 mm/sup 2/, 70% of the total area of a typical unshared transceiver chip. The transmitting and receiving modes of operation show -3-dB bandwidths of 2.2 and 2.4 GHz and electrical isolations of -28 and -40 dB, respectively.     

PWM digital pixel sensor based on asynchronous self-resetting scheme

In this letter, a pulse-width modulated digital pixel sensor is presented along with its inherent advantages such as low power consumption and wide operating range. The pixel, which comprises an analog processor and an 8-bit memory cell, operates in an asynchronous self-resetting mode. In contrast to most CMOS image sensors, in our approach, the photocurrent signal is encoded as a pulse-width signal, and converted to an 8-bit digital code using a Gray counter. The dynamic range of the pixel can be adapted by simply modulating the clock frequency of the counter. To test the operation of the proposed pixel architecture, an image sensor array has been designed and fabricated in a 0.35-/spl mu/m CMOS technology, where each pixel occupies an area of 45/spl times/45 /spl mu/m/sup 2/. Here, the operation of the sensor is demonstrated through experimental results.     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

A fast 256K DRAM designed for a wide range of applications

A 256K DRAM designed for a variety of organizations and operation modes is described. The chip may be organized as 64K/spl times/4, 128K/spl times/2, or 256K/spl times/1. Four data I/O buffers are selectable by gate signals. Besides the standard RAM mode, it may be operated in the page mode, in the parallel or serial buffer mode, and in a combination of page and serial buffer modes. With these options, the design covers a wide range of applications. RAS/CAS access times are 80.55 ns. In the combined page and serial buffer mode, a data rate of up to 50 MHz is possible. The chip is built in metal-gate n-channel technology with 2-/spl mu/m minimum line width and two metal interconnection planes.     

New miniature 15-20-GHz continuous-phase/amplitude control MMICs using 0.18-/spl mu/m CMOS technology

The design and performance of two new miniature 360/spl deg/ continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18-/spl mu/m CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm /spl times/ 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm /spl times/ 0.82 mm. To the best of the authors' knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360/spl deg/ phase-control range above 5 GHz reported to date.     

A biomorphic digital image sensor

An arbitrated address-event imager has been designed and fabricated in a 0.6-/spl mu/m CMOS process. The imager is composed of 80 /spl times/ 60 pixels of 32 /spl times/ 30 /spl mu/m. The value of the light intensity collected by each photosensitive element is inversely proportional to the pixel's interspike time interval. The readout of each spike is initiated by the individual pixel; therefore, the available output bandwidth is allocated according to pixel output demand. This encoding of light intensities favors brighter pixels, equalizes the number of integrated photons across light intensity, and minimizes power consumption. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel. The array, on the other hand, produced a dynamic range of 120 dB (under uniform bright illumination and when no lower bound was placed on the update rate per pixel). The dynamic range is 48.9 dB value at 30-pixel updates/s. Power consumption is 3.4 mW in uniform indoor light and a mean event rate of 200 kHz, which updates each pixel 41.6 times per second. The imager is capable of updating each pixel 8.3K times per second (under bright local illumination).     

Wide dynamic range snapshot APS for ultra low-power applications

A novel wide dynamic range (WDR) snapshot active pixel sensor for ultra-low power applications is presented. The proposed imager allows capturing of fast moving objects in the field of view and provides WDR by applying adaptive exposure time to each pixel, according to the local illumination intensity level. Driven by low-power dissipation requirements, the proposed pixel is operated by dual low voltage supplies (1.2 and 1.8 V) and utilizes an advanced low-power sensor design methodology. A test chip of a 32*32 array has been implemented in a standard 0.35-/spl mu/m CMOS technology. A single pixel occupies 18*32 /spl mu/m area and is expected to dissipate 18.5 nW at video rate. System architecture and operation are discussed and simulation results are presented.     

A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-/spl mu/m CMOS technology

An ultra-wideband mixer using standard complementary metal oxide semiconductor (CMOS) technology was first proposed in this paper. This broadband mixer achieves measured conversion gain of 11 /spl plusmn/ 1.5 dB with a bandwidth of 0.3 to 25 GHz. The mixer was fabricated in a commercial 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation. It also presented better gain-bandwidth-product performance compared with that of GaAs-based HBT technologies. The chip area is 0.8 /spl times/ 1 mm/sup 2/.     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.     

An experimental 4-Mbit CMOS DRAM

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.     

A new type of demountable optical device for coupling single-mode planar waveguides to a multifiber array using passive alignment

A novel demountable optical device is developed for coupling single-mode waveguides to a multifiber array using passive alignment. This device is fabricated by forming V-grooves on a waveguide chip and precisely molding both end portions of the chip. The 1/spl times/8 coupling device exhibits a low insertion loss of 10.7 dB and a small loss change of /spl plusmn/0.2 dB for 100 reconnections.