共查询到19条相似文献,搜索用时 265 毫秒
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对FPGA和CPLD器件的逻辑结构和性能进行比较,阐明电子系统设计中FPGA/CPLD器件选型时应注意的基本原则,并论述FPGA/CPLD与以单片机、DSP为代表的嵌入式系统及SoPC,ASIC等技术相互融合的技术特征和趋势,充分证明FPGA/CPLD器件将与嵌入式系统、SoC/ASIC等技术进一步广泛融合,在广阔的电子设计领域发挥不可忽视的作用。可为以FPGA/CPLD为代表的可编程逻辑器件的扩展应用提供借鉴。 相似文献
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一.可编程逻辑器件的设计流程
可编程逻辑器件的设计流程如图1所示,主要包括设计输入、综合、CPLD/FPGA器件适配、仿真和编程下载等。 相似文献
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介绍应用CPU和现场可编程逻辑阵列(FPGA)/复杂可编程逻辑器件(CPLD)结合设计电子系统的优势.基于AT89C51单片机系统实现FLEK10K的在线可重配置(ICR),PC机和AT89C51串行通信实现在线升级,PC机下载配置实现在线调试.采用直接数字频率合成(DDS)技术,实现波形发生器.应用电子设计自动化(EDA)技术,以FPGA/CPLD器件为核心,采用FPGA设计的DDS不仅可方便地实现各种比较复杂的调频、调相和调幅功能,而且具有良好的实用性.文中给出了系统的工作原理和设计方法. 相似文献
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<正> 现场可编程门阵列(FPGA)是可编程器件。与传统逻辑电路和门阵列(如PAL、GAL及CPLD器件)相比,FPGA具有不同的结构,FPGA利用小型查找表(16×1RAM)来实现组合逻辑;每个查找表连接到一个D触发器的输入端,触发器再来驱动其它逻辑电路或驱动I/O,由此构成了既可实现组合逻辑功能又可实现时序逻辑功能的基本逻辑单元模块;这些模块间利用金属连线互相连接或连接到I/O模块。FPGA的逻辑是通过 相似文献
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开发多课程综合实验设备加强创新能力培养 总被引:4,自引:2,他引:2
利用CPLD/FPGA内部强大的互连技术及模拟可编程器件的可编程性,实现模拟电子、数字电子、单片机、CPLD/FPGA等多课程实验教学,提高学生的综合素质及创新能力的培养。 相似文献
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设计研制了一款适用于数据通路的10万门容量的FPGA器件FDP100K(FDP:FPGA for Data-Path),其主要特点为:可编程逻辑单元结构不同于国际上已有的可编程逻辑单元结构,是一种新颖的基于查询表LUT和多路选择器MUX的混合结构;连线资源结构采用新颖的层次式布线结构,提供高度灵活的布线能力.芯片采用SMIC 0.35 μm CMOS工艺,包含1024个可编程逻辑单元和128个可编程IO单元.芯片配合自主开发的软件系统FDE(FPGA Development Environment)进行测试,结果表明:FDP100K芯片的可编程逻辑单元功能正常;芯片的各种连线资源功能正常;可以准确地实现数据通路型电路和其他类型的电路的功能. 相似文献
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In just the last few years, the personal electronics market has seen explosive growth. Along with entirely new consumer products, there are concomitant developments in computer engineering. Although the system on a chip (SoC) concept is mature, the increasing density and sophistication of the field programmable gate array (FPGA) is introducing new design methodologies and higher levels of integration. While a single FPGA alone can implement an entire microprocessor system, manufacturers also provide the option of having an actual microprocessor integrated into the FPGA chip. In both situations the FPGA fabric (defined in this article as a two dimensional array of identical logic blocks in an interconnect resource) implements custom peripherals and other devices. The FPGA has essentially become a breadboard, allowing for truly rapid product development. 相似文献
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A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 × 30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently. 相似文献
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为了满足对开关电源实时测量的应用需求,设计了一种基于FPGA和DSP的多路同步实时数据采集系统,该系统利用可编程逻辑器件FPGA将多个功能模块连接在一起,完成了对A/D转换芯片及双口等模块的控制,同时利用DSP进行高速数据运算和处理;文中给出了系统硬件原理框图,并结合系统的设计方案对其中的主要功能模块进行了阐述;该多路同步数据采集系统具有实时性强、集成度高、扩展性灵活等特点。 相似文献
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Wu Fang Zhang Huowen Lai Jinmei Wang Yuan Chen Liguang Duan Lei Tong Jiarong 《半导体学报》2009,30(6):132-137
This paper presents a universal field programmable gate array (FPGA) programmable routing circuit,focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable. 相似文献
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文章介绍了一种可远程接收的智能视频字幕显示控制电路。该电路采用MCS8051单片机作为控制核心,EPF7064S可编程逻辑器件产生所需时序及信号,W9952QP视频解码器产生视频信号。着重阐述了可编程逻辑器件内部逻辑电路的设计。 相似文献
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LZW改进压缩算法的FPGA实现 总被引:1,自引:0,他引:1
随着实时监控系统的发展,大容量高速数据采集与传输技术不断取得新的进展,针对当前数据传输采用硬件实现速度快,但难以进行数据处理,而软件能实现很多算法但处理速度稍显逊色的不足,采用了LZW压缩算法及其改进算法,并将该算法在可编程逻辑器件FPGA上进行了实现,通过仿真,验证了设计的正确性,提高了数据传输速度。 相似文献
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