模拟集成电路模块生成系统的电气性能研究

文章对模拟集成电路模块生成系统的电气性能进行了系统研究,如MOS晶体管失配量、栅极RC常数、寄生电容及路径载流等.并将各电气参数的估算值与具体应用相结合,控制不同限制条件及应用背景下的模块生成,增强电路设计的可靠性.采用该电气性能驱动的模块生成系统,已经辅助设计出多个高性能集成运算放大器、模拟开关等芯片版图.     

基于模拟集成电路BIST的ARMA模块设计

针对模拟集成电路在线测试困难的特点,本文基于BIST结构对模拟集成电路的测试提出了一种新的测试方案,这种算法在测试电路中易于实现,并且容易嵌入到待测芯片中,为模拟集成电路可测试性设计提出了一种新的测试结构和测试算法。     

一种新的模块自动生成技术及其系统

本文提出一种适于ＣＭＯＳ集成电路的柔性模块生成器，该系统将电路描述按照一定的约束条件（布图面积即模块高度和宽度或宽长比，ＰＩＮ的位置，最大延迟）自动转换成版图．本文采用了一种二维的柔性模块布图模型，使系统具有一定的灵活性．因此，该系统不仅可作为一种自动建库的工具，也可作为一个晶体管编译器为一个分级式的布图系统按照实际的布图要求生成底层的宏单元或库中没有的宏单元模块．     

具有边界约束的LSI模块版图自动生成系统

本文介绍了一个具有边界约束的大规模集成电路模块版图自动生成系统（ＡＭＧＣ）。ＡＭＧＣ的输入为模块的电路网表，输出为模块的ＣＭＯＳ版图数据。由ＡＭＧＣ自动生成的版图既符合用户的设计规则，也符合模块输入输出端口位置及长宽比等用户给出的约束条件。     

双极模拟集成电路版图识别的模式识别算法

双极模拟ＩＣ在广泛应用于个人移动通信ＲＦＩＣ中占有重要地位。双极模拟ＩＣ版图识别与验证是其ＣＡＤ研究的重要内容之一。基于模式识别和专家系统的思想,提出了一种双极模拟ＩＣ版图识别的模式识别算法。该方法定义了五种基本版图图形关系,在此基础上构造了版画图技术向量,建立了算法系统及识别系统。该识别算法的优点在于与具体工艺过程无关,从而使识别过程完全系统化。实验表明,该识别系统有效、准确、可靠。     

硅模拟集成电路

本文综述了国内外模拟集成电路的发展动态，叙述了国内模拟集成电路与国外的主要差距，针对国内的具体情况，提出了发展我国模拟集成电路的观点对策。     

模块结构的SOC集成电路测试系统

根据不完全的统计,从1980年代开始集成电路的工艺快速更新换代,集成度按摩尔定律每18个月增加一倍,此增长势头将会延续至2010年。相应生产每晶体管成本从0.5美分下降至200年的0.001美分,而测试每个晶体管成本只从0.4     

基于BP神经网络的大规模电路模块级故障快速诊断方法

根据大规模电路故障诊断网络撕裂法和交叉撕裂搜索方法,采用基于误差反向传播算法的多层前向神经网络(BP神经网络)记载多次撕裂信息,提出了一种新型基于BP神经网络的大规模电路模块级快速诊断方法。该方法能快速有效地并行处理定位故障模块,具有测前工作量小,实时诊断性强等优点。     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

集成电路低功耗设计方法

针对当前集成电路低功耗的需求,对当前几种常用的低功耗设计方法和技术进行探讨,包括算法优化、工艺优化、版图优化、门级优化等,从而为当前继承电路优化提供借鉴参考。     

器件参数宏模型的精确建立及其在模拟集成电路性能建模与优化中的应用

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presnted to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit's characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs.The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

LM算法在模拟电路故障诊断中的研究

模拟电路的特征提取和分类识别可以通过在神经网络训练中应用最多的BP算法来实现。由于标准BP算法的收敛速度较慢、在训练中效率不高的缺点,文中提出了一种快速稳定的Levenberg-Marquardt(LM)算法来改进BP算法。Pspice与MATLAB相结合的仿真结果表明该算法能有效地诊断模拟电路故障,且具有更好地收敛性,适用于神经网络。     

Automated topology synthesis of analog and RF integrated circuits: A survey

The puzzle of automatically synthesizing analog and radio frequency (RF) circuit topology has not yet been offered with an industrially-acceptable solution although endeavors still continue to seek a conquest in this area. This survey provides a comprehensive study of the techniques utilized for this purpose. The existing methods are analyzed from four different viewpoints, namely, structural view, conceptual view, implementation view, and application view. Different schemes are perused with their advantages and drawbacks discussed in the context of balanced performance between configuration-space coverage and search efficiency. Some prospective trends are pointed out to shed light on the upcoming research activities.     

A performance-driven placement tool for analog integrated circuits

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples     

倒装芯片集成电力电子模块寄生参数的建模

采用球栅阵列芯片尺寸封装技术和倒装芯片(Flip Chip,FC)技术构建了半桥集成电力电子模块(Integrated Power Electronics Module,IPEM),半桥FC-IPEM实现三维封装结构。采用阻抗测量法提取模块寄生电感和寄生电容,建立模块的寄生参数模型,对模块进行电气性能测试。结果表明:半桥FC-IPEM构成的同步整流Buck变换器输出滤波电感中的电流波动幅度小于0.6A。