Two-wire bridge-to-frequency converter

An integrated two-wire bridge-to-frequency converter is presented for use as a remote-signal conditioner for sensor bridges such as strain-gauge bridges of platinum-wire temperature-sensing bridges. The converter has a sensitivity on the order of 1 Hz per 1-/spl mu/V/V relative bridge output. A center frequency of 10 kHz allows the application of an untrimmed bridge with an imbalance up to /spl plusmn/10000 /spl mu/V/V. The instability is less than 10/SUP -4/ per Kelvin and per 1-V supply-voltage variation. The untrimmed transfer inaccuracy is lower than 1%. The linearity error is lower than 0.01%. Different bridge readout functions can be chosen by different circuit configurations. The converter can be connected to a single supply voltage. The frequency output is modulated on the supply current. The supply voltage is 12-24 V.     

High-performance low-power CMOS memories using silicon-on-sapphire technology

Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-/spl mu/m channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 /spl mu/W/bit (quiescent) and 10 /spl mu/W/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 /spl mu/W/bit.     

A 14-bit monotonic NMOS D/A converter

A new configuration of a 14-bit digital-to-analog (D/A) converter has been fabricated as an experimental monolithic NMOS chip. The concept utilizing two cascaded resistor strings delivers an inherent 14 bit monotonicity and a static voltage output signal. The small chip size of about 8.5 mm/SUP 2/ and the saving of external components make the converter applicable for low-cost high-resolution control loop systems. A modified test chip is also described which has been provided as a step into the field of accurate monolithic converters needed for digital audio systems. A voltage output settling time less than 10 /spl mu/s and a linearity at the 12 bit level have been achieved.     

An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction

An integrated adaptive-output switching converter is presented. This converter adopts one-cycle control for fast line response and dual error correction loops for tight load regulation. A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process. The design accommodates both continuous and discontinuous conduction operations. To further enhance the efficiency, dynamic loss control on the power transistors is proposed to minimize the sum of switching and conduction losses. The design can be extended to other dc-dc and ac-dc conversions. The prototype of the buck converter was fabricated with a standard 0.5-/spl mu/m digital CMOS process. Experimental results show that the converter is well regulated over an output range of 0.9-2.5 V, with a supply voltage of 3.3 V. The tracking speeds are 12.25 /spl mu/s/V for a 1.6-V step-up output change and 13.75 /spl mu/s/V for a 1.6-V step-down output change, respectively, which are much faster than existing counterparts. Maximum efficiency of 93.7% is achieved and high efficiency above 75% is retained over an output power ranging from 10 to 450 mW.     

A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.     

An ultralow-power switched opamp-based 10-B integrated ADC for implantable biomedical applications

This paper describes an ultralow-power switched opamp-based integrated analog-to-digital converter (ADC) for cardiac pacemakers applications. The ADC consumption, measured on 10 chip samples and averaged, is 8.18 /spl mu/W (stand-by value: 1 nW) for the analog part and of 9.71 /spl mu/W (5 nW) for the digital one, using a supply battery of 2.8 V. The converter has a resolution of 10-b, its typical operating clock frequency is 32 KHz (2.9 KS/s sampling rate) and is able to reach the same resolution at 2 V (0.7 KS/s sampling rate), with a dissipation of 1 /spl mu/W and 1.3 /spl mu/W for analog and digital part, respectively.     

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.     

High breakdown Voltage undoped AlGaN-GaN power HEMT on sapphire substrate and its demonstration for DC-DC converter application

Undoped AlGaN-GaN power high electron mobility transistors (HEMTs) on sapphire substrate with 470-V breakdown voltage were fabricated and demonstrated as a main switching device for a high-voltage dc-dc converter. The fabricated power HEMT realized a high breakdown voltage with a field plate structure and a low on-state resistance of 3.9 m/spl Omega//spl middot/cm/sup 2/, which is 10 /spl times/ lower than that of conventional Si MOSFETs. The dc-dc converter operation of a down chopper circuit was demonstrated using the fabricated device at the input voltage of 300 V. These results show the promising possibilities of the AlGaN-GaN power HEMTs on sapphire substrate for future switching power devices.     

A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.     

A monolithic 14-bit D/A converter

A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described. Over a temperature range from -50/spl deg/ to 70/spl deg/C the nonlinearity is less than one-half least significant bit (/SUP 1///SUB 2/LSB). Dynamic tests show a distortion at a level of about -90 dB with respect to the maximum sinewave output. Nearly no glitches are found, so the converter can be operated without a deglitcher circuit. The chip, with a size of 3.1/spl times/3.2 mm, contains all elements needed, except the output amplifier and digital input latches.     

A self-calibrating 15 bit CMOS A/D converter

A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.     

A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies

A 1-V integrated CMOS current-mode boost converter implemented in a standard 3.3/5-V 0.6-/spl mu/m CMOS technology (V/sub TH//spl ap/0.85 V), providing power-conversion efficiency of higher than 85% at 100-mA output current, is presented in this paper. The high-performance boost converter is successfully developed due to three proposed low-voltage circuit structures, including an inductor-current sensing circuit for current-mode operation with accuracy of higher than 94%, a precision V-I converter for compensation-ramp generation in current-mode control, and a VCO providing supply-independent clock and ramp signals. Moreover, a proposed startup circuit enables proper converter startup within a sub-1-V supply condition.     

A low-power SRAM using hierarchical bit line and local sense amplifiers

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.     

Ultra-low-power variable-resolution successive approximation ADC for biomedical application

An ultra-low-power variable-resolution successive approximation analogue-to-digital converter (ADC) is presented. A novel binary search algorithm architecture is proposed to replace the conventional digital-to-analogue converter to significantly reduce system area and power consumption. The proposed ADC consumes less than 22.2 /spl mu/W of power at a conventional 2 V battery supply with a sampling rate of 200 samples/s, and standby power consumption of less than 1 /spl mu/W.     

An 8-MHz CMOS subranging 8-bit A/D converter

A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.     

A two-phase plasma-coupled static shift register

In designing an experimental 2-bit plasma-coupled shift register, fabricated with standard bipolar technology, it is shown that a simplification of the existing plasma-coupled device (PCD) concept by omission of the double base diode not only decreases the power dissipation and increases the ease of fabrication, but also increases the attractive simplicity of the basic cell. The average power dissipation of the new device is 200 /spl mu/W/bit at a clock frequency of 3 MHz. The bit density is 135 bit/mm/SUP 2/ with 10-/spl mu/m spacing between interconnection lines 10 /spl mu/m in width. A hypothetical layout with dielectric isolation and closer tolerances results in a bit density of 900 bit/mm/SUP 2/ and an estimated power dissipation of 80 /spl mu/W/bit.     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.     

一种带接口的CMOS10位电流型乘法D／A转换器

介绍了一种带接口的单片ＣＭＯＳ１０位电流型乘法Ｄ／Ａ转换器的设计及工作方式。着重阐述逻辑电平转换、控制逻辑的结构设计及其工作方式。在不修调电阻网络的情况下，该Ｄ／Ａ转换器在５Ｖ、１５Ｖ下，其线性误差、微分误差、满刻度误差均能达到１０位精度     

Circuit techniques for achieving high speed-high resolution A/D conversion

A 12 bit, 25 /spl mu/s, analog-to-digital converter has been successfully integrated on two process-compatible junction-isolated chips. One chip contains a 200 ns digital-to-analog converter with reference, while the other contains the comparator, an I/SUP 2/L successive-approximation register, multiplexed three-state T/SUP 2/L output buffers, and a controller designed to interface directly to several common microprocessors. The authors describe several innovations which allow this degree of integration at the 12 bit accuracy level.