Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as "silicon-on-insulator" and other "on-insulator" substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed     

Model-free estimation of defect clustering in integrated circuitfabrication

This paper describes a model-free method for estimating some yield metrics that are used to track integrated circuit fabrication processes. Our method uses binary probe test data at the wafer level to estimate the size, shape and location of large-area defects or clusters of defective chips. Unlike previous methods in the yield modeling literature, our approach makes extensive use of the location of failing chips to directly identify clusters. An important by product of this analysis is a decomposition of wafer yield that attributes defective chips to either large- or small-area defects. Simulation studies show that our procedure is superior to the time-honored windowing technique for achieving a similar breakdown. In addition, by directly estimating defect clusters, we can provide engineers with a greater understanding of the manufacturing process. It has been our experience that routine identification of the spatial signatures of clustered defects and associated root-cause analysis is a cost-effective approach to yield and process improvement     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Yield improvement using statistical analysis of process dates

Rapid yield improvement is necessary in modern wafer fabrication facilities to ensure profitability of huge investments. Statistical analysis of data is a valuable method for improving yield. Usual methods like statistical process control (SPC), designs of experiments (DOE) and mapping analysis are necessary, but not sufficient because of process complexity. This paper presents a new statistical approach for solving yield issues when the root cause comes from a failure at a single process stage. The advantage of this approach is the only data required are the process dates of the lots at each process stage and the probe results. Three different methods have been tested to solve these issues. Only one of them is detailed in this paper. The efficiency of this method is demonstrated on two real yield issues where the defective stage is known.     

Benefits of real-time, in situ particle monitoring in productionmedium current implantation

Real-time free particle measurements in the loadlocks of a production medium current implanter have been conducted. These measurements correlate to both surface scans and electrical test yield. They suggest that episodic particle generating events that impact yield occur frequently and that particle levels are considerably higher when product wafers are run than when monitor wafers are run. The data correlate to monitor wafer surface counts, allowing the real-time monitor to be used in equipment requalification. The data also provide a real-time plot of machine utilization and performance and can be useful in identifying variations in both the implant process and feeder processes. It is concluded that a strategy of in situ, real-time sampling combined with test wafer monitoring can lead to improved particle control     

InSb晶片清洗研究

随着红外探测器件制备工艺的不断发展,人们对InSb晶片表面质量的要求也越来越高,但是晶片在生产过程中不可避免地会引进各种杂质。研究了一种利用兆声超声并结合药液去离子水清洗InSb晶片的方法,并对清洗后的InSb晶片进行了表面颗粒度、表面有机物和表面粗糙度等方面的测量。实验结果表明,该方法能够有效去除InSb晶片表面的颗粒、有机物和金属离子杂质,但是也会略微增大晶片表面的粗糙度。     

Photoelastic stress evaluation and defect monitoring in 300-mm-wafer manufacturing

Process monitoring and tool characterization on product wafers require rapid non-contact and non-destructive evaluation methods. Because all process steps are more or less related to stress in the crystal, the photoelastic stress evaluation by infrared polarimetry is a suitable method for process screening both in wafer and IC manufacturing. It is shown that the full wafer imaging by scanning infrared depolarization can be applied to different steps of wafer manufacturing. After a short introduction into the method and technical realization of on-line photoelastic measurements, the concept of defect-related stress monitoring and process screening is demonstrated for slicing, grinding, lapping, etching, polishing and thermal treatment.     

A directed-graph classifier of semiconductor wafer-test patterns

A technique for training an expert system for semiconductor wafer fabrication process diagnosis is described. The technique partitions an existing set of electrically tested semiconductor wafers into groups so that all wafers within each group have similar spatial distributions of the electrical test data across selected die sites. The spatial distribution of test data from the selected die sites on each wafer is referred to as the test pattern of that wafer. A directed graph that is developed by the partitioning algorithm then efficiently classifies a new incoming wafer to one of the groups established during partitioning on the basis of its test pattern. The distribution of known processing histories of wafers within the group to which the new incoming wafer is classified provides a provisional diagnosis of the incoming wafer's process history     

Yield degradation of integrated circuits due to spot defects

Economy of integrated circuit fabrication in the presence of quasi-randomly distributed spot defects is described. The distribution of the defects is represented in terms of density and modeled as follows : 1) they are randomly distributed within a limited area; 2) the density in a wafer changes concentrically; and 3) the density is normally distributed from wafer to wafer with uniform deviation throughout a wafer. The yield degradation phenomenon due to such defects has been analyzed using a computer simulation technique. The effect of density variations in a wafer and between wafers has been mainly investigated. An extensive numerical study leads to the following conclusions. 1) The deviation of the yield versus chip-area relation from the simple exponential law is influenced more greatly by the nonuniform defect distribution in a wafer than by the density variation between wafers. 2) The increase of average yield due to the density variation between wafers is sometimes offset by the decrease of the accuracy in yield prediction. Process stabilization is essential for the economical production of a few large-scale chips.     

The nature of particle generation in vacuum process tools

Particle levels in a variety of VLSI process tools are shown to have relatively constant baselines punctuated by short bursts. That these excursions decay rapidly while the baseline remains constant suggests that a strong feedback mechanism exists to hold particle levels in equilibrium. It is shown that this equilibrium is a function of process and wafer conditions and can be disrupted, for example, by running monitor wafers instead of product wafers. This implies that process monitoring methodologies using monitor wafers must be used with caution. The bursts are shown to have a strong potential yield effect when multiple process steps are considered. This effect is strongest when products are early in their life cycle or relatively sensitive to defects     

Dynamic load balancing among multiple fabrication lines through estimation of minimum inter-operation time

We propose a load balancing method which balances all processing operations of products among multiple semiconductor wafer fabrication lines (fabs) by using predictive scheduling results. Through a simulation experiment we confirmed that the proposed method enabled improved load balancing (compared to conventional methods) among multiple fabrication lines each of which can independently fabricate wafers and has different wafer processing capacity. The load balancing feature effectively reduces the waiting time at each process step and the lead time of all products in multiple fabs. Another promising application of the proposed method is performance evaluation of automated material handling systems (AMHS) in terms of inter-operation time, and we have used the method to evaluate the transportation efficiency of actual fabs.     

The binomial test: a simple tool to identify process problems

The yield distribution of a batch of wafers is an indicator of the type and behavior of defect sources in the manufacturing process. In a stable process, defects generated by these sources are evenly and randomly distributed, repetitive from wafer-to-wafer. The yield distribution of wafers manufactured in such an environment follows the binomial distribution. If, on the other hand, wafers contain defects with systematic patterns that repeat from wafer-to-wafer, the yield distribution tends to be narrower than the binomial distribution. For defect sources that generate systematic wafer-to-wafer variations, the yield distribution widens if compared with the binomial distribution. The binomial distribution can be calculated from the mean yield and the number of dice per wafer. Thus, comparing the actual yield distribution with the corresponding binomial distribution (binomial test) gives the yield improvement engineer a simple first-order indicator of the behavior of defect sources. Since wafer yield data is routinely available from functional production tests, the binomial test can be performed with existing data. This paper describes the principle and use of the binomial test using visual analysis on graphical yield plots of simulated and actual production wafers     

Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration

Three-dimensional integrated circuit technology with through-silicon vias offers many advantages, including improved form factor, increased circuit performance, robust heterogenous integration, and reduced costs. Wafer-to-wafer integration supports the highest possible density of through-silicon vias and highest throughput; however, in contrast to die-to-wafer integration, it does not benefit from the ability to bond only tested and diced good die. In wafer-to-wafer integration, wafers are entirely bonded together, which can unintentionally integrate a bad die from one wafer to a good die from another wafer reducing the yield. In this paper, we propose solutions that maximize the yield of wafer-to-wafer 3-D integration, assuming that the individual die can be tested on the wafers before bonding. We exploit some of the available flexibility in the integration process, and propose wafer assignment algorithms that maximize the number of good 3-D ICs. Our algorithms range from scalable, fast heuristics to optimal methods that exactly maximize the yield of wafer-to-wafer 3-D integration. Using realistic defect models and yield simulations, we demonstrate the effectiveness of our methods up to large numbers of wafer stacks. Our results demonstrate that it is possible to significantly improve the yield in comparison to yield-oblivious wafer assignment methods.      

0.2μmT形栅技术在10Gbps激光驱动电路研制中的应用

0.2μm T形栅制作技术在10 0 mm Ga As激光驱动电路芯片研制中获得了成功的应用.优化的栅制作工艺保证了形貌良好的栅线条,获得了优良的晶体管直流参数和高频性能.栅工艺重复性好,整片内器件性能均匀一致,确保了电路的成功研制.实际电路测试结果表明,在10 0 mm Ga As片上制备的PHEMT驱动电路的芯片测试合格率达到70 %以上,可靠性良好     

Due-date based scheduling and control policies in a multiproductsemiconductor wafer fabrication facility

This paper focuses on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows. For lot release control, it is necessary to determine the type of a wafer lot and the time to release wafers into the wafer fab, while it is necessary to determine sequences of processing waiting lots in front of workstations for lot scheduling. New dispatching rules are developed for lot release control and scheduling considering special features of the wafer fabrication process. Simulation experiments are carried out to test the dispatching rules. Results show that lot release control and lot scheduling at photolithography workstations are more important than scheduling at other workstations. Also, it is shown that new dispatching rules work better in terms of tardiness of orders than existing rules such as the EDD (earliest due date) rule and other well-known dispatching rules for multimachine scheduling     

基于神经网络方法的半导体生产工艺优化

以提高生产成品率为目标,利用神经网络的非线性和容错性,对半导体芯片生产过程进行了分析和优化,具体内容如下：（１）使用神经网络方法建立模型,确定生产线上工艺参数和成品率之间的映射关系,构造以工艺参数为输入,成品率为输出的多维函数曲面．（２）对上述多维函数曲面进行搜索,搜索成品率最高的最优点,以该最优点的工艺参数值为依据确定工艺参数的规范值．（３）对工艺参数规范进行优化,在实际生产工艺中反复实践,直至达到提高成品率的目的．生产实践证明,神经网络的分析结果是合理的．根据神经网络分析提出的优化建议,有效地提高了工     

Prediction of wafer state after plasma processing using real-timetool data

Empirical models based on real-time equipment signals are used to predict the outcome (e.g., etch rates and uniformity) of each wafer during and after plasma processing. Three regression and one neural network modeling methods were investigated. The models are verified on data collected several weeks after the initial experiment, demonstrating that the models built with real-time data survive small changes in the machine due to normal operation and maintenance. The predictive capability can be used to assess the quality of the wafers after processing, thereby ensuring that only wafers worth processing continue down the fabrication line. Future applications include real-time evaluation of wafer features and economical run-to-run control     

Methods to Quantify the Detection Probability of Killing Defects

Two methods are presented to quantify the killing defect detection probability, or capture rate, of inline defect inspections. The first method uses yield impact and kill ratio of defects above a given size. By comparing the theoretical, critical-area based dependence between the yield impact and the kill ratio of defects above a given size, with the dependence as found from defect–yield correlation on product wafers, an estimate can be made of the fraction of yield impact explained by detected defects. The second method uses conventional defect–yield correlation. By plotting wafer level yield of clean die against the yield impact found by defect–yield correlation, it is possible to estimate the yield impact of undetected defects.     

Minimum test chip sample size selection for characterizing process parameters

A method for determining a test-chip sample size to estimate effectively the electrical parameter distributions on an integrated circuit wafer is presented. This method gives relations among sample size and the figure of merit for four statistical techniques (trimmed mean, biweighted mean, median, and arithmetic mean) by which estimates are calculated. To demonstrate its use, the method has been applied to the evaluation of a CMOS fabrication process. Measurements on wafers completely patterned with identical test chips were used to determine actual parameter distributions for an entire wafer (true parameter values). Estimates of true parameters were determined using a site-selection plan which is representative of sampling plans used in industry. The four statistical techniques were used to compute estimates for electrical parameters and their respective figures of merit. These estimates were compared with the true parameter values determined from testing all test chips on the wafer.