AC electroosmotic microconcentrator using a face-to-face,asymmetric electrode pair with expanded sections in the bottom electrode

An AC electroosmotic (AC-EO) microconcentrator using a face-to-face, asymmetric electrode pair with expanded sections in the bottom electrode is proposed in this study. The electrode pair of the AC-EO microconcentrator is composed of a larger top electrode (30 mm × 60 mm) and a bottom electrode (containing three slim electrodes and a triangular electrode). In the expanded section at the connection of a slim electrode and the triangular electrode, an electroosmosis flow transports test samples far away from the triangular electrode to the stagnation zone inside the triangular electrode through the slim electrode for concentration. On the three sides of the triangular electrode, vortices bring test samples surrounding the triangular electrode to the stagnation zone. By these two electroosmosis flow fields, the microconcentrator can concentrate test samples near and far from the triangular electrode to its central area, achieving a highly efficient sample concentration. The measured concentration distribution in the vertical electrode direction by confocal microscopy indicates that the concentration process occurs above the electrode surface. The capability of the proposed AC-EO concentrator in the repeated concentration and release of test samples is verified by a reversible switch test. The performance of the proposed AC-EO concentrator in concentrating latex particles and T4 GT7 DNA is better than those reported in the literature under similar average electric field strength. The fluorescence enhancement factor is 3.9–9.1 times better when concentrating latex particles, and the concentration enhance factor is 1.4–5.7 times better when concentrating T4 GT7 DNA.     

Non-destructive on-chip imaging flow cell-sorting system for on-chip cellomics

We have developed a non-destructive imaging flow cell-sorting system using an ultra-high-speed camera (shutter speed of 1/10,000 s) with a real-time image analysis unit and a poly(methyl methacrylate) (PMMA)-based disposable microfluidic chip for single-cell-based on-chip cellomics. It has a 3-D micropipetting device that supports fully automated sorting and collection of samples. The entire fluidic system is implemented in a disposable plastic chip, enabling biological samples to be lined up in a laminar flow using hydrodynamic focusing. Its optical system enables direct observation-based cell identification using specific image indexes and phase-contrast/fluorescence microscopy, real-time image processing. It has a non-destructive, wider dynamic range, sorting procedure using mild electrostatic force in a laminar flow; agarose gel electrodes are used to prevent electrode loss and electrolysis bubble formation. The microreservoir used for recultivating collected target cells is contamination-free. An integrated ultra-high-speed droplet polymerase chain reaction measurement module is used for DNA/mRNA analysis of the collected target cells. This system was used to separate cardiomyocyte cells from a mixture of various cells. All the operations were automated using the 3-D micropipetting device. The results demonstrate that this imaging flow cell-sorting system is practically applicable for biological research and clinical diagnosis.     

Microfluidic chips for cells capture using 3-D hydrodynamic structure array

Microfluidic chips were designed and fabricated to capture cells in a relative small volume to generate the desired concentration needed for analysis. The microfluidic chips comprise three-dimensional (3-D) cell capture structures array fabricated in PDMS. The capture structure includes two layers. The first layer consists of spacers to create small gap between the upper layer and glass. The second layer is a sharp corner U-shaped compartment with sharp corners at the fore-end. And another type capture structure with Y-shaped fluidic guide has been designed. It was demonstrated that the structures can capture cells in theory, using Darcy–Weisbach equation and COMSOL Multiphysics. Then yeast cell was chosen to test the performance of the chips. The chip without fluid guides captured ~1.44 × 10⁵ cells and the capture efficiency was up to 71 %. And the chip with fluid guides captured ~5.0 × 10⁴ cells and the capture efficiency was ~25 %. The chip without fluid guides can capture more cells because the yeast cells in the chip without fluid guides are subject to larger hydrodynamic drag force.     

Use of a gradient-generating microfluidic device to rapidly determine a suitable glucose concentration for cell viability test

We successfully determined a suitable glucose concentration for endothelial cells (ECs) using a gradient-generating microfluidic chip and a micro-stamper that were fabricated using micro-electro-mechanical systems (MEMS) technology. Our strategy was to generate a stable concentration gradient in the observation area based on a microfluidic network and micro-mixers, which produced a concentration gradient under various flow rates. The areas for cell adhesion were delineated on a glass slide with a micro-stamper using the micro-contact printing (μCP) method. We also discuss which glucose concentration gradients are suitable for cell viability test (i.e., 0–0.2%, 0.05–0.15%, and 0.06–0.17%). After examining various concentration gradients, the suitable glucose concentration for EC’s viability test was determined to range from 0.077% (4.2 mM) to 0.147% (8.16 mM). Higher or lower concentrations caused the ECs to atrophy or die. In this study, we describe a gradient-generating microfluidic chip that can be used to produce various drug concentrations for multi-concentration tests.     

基于IEC61850-9-2合并单元的研究与设计

介绍了一种智能变电站合并单元的设计方案,采用现场可编程逻辑阵列（FPGA）作为硬件框架,充分利用FPGA的模块化编程和多任务处理的特点,通过在FPGA芯片上配置NiosII软核处理器和相关接口,完成合并单元采样脉冲同步、数据采集及处理,将数据按照IEC61850-9-2标准组帧通过以太网与过程层设备通信发送至过程层设备。运用MMS Ethereal软件对本合并单元输出的电压、电流信号进行测试,结果表明该合并单元所送数据与接收数据一致,符合9-2标准。本装置可以实现了合并单元多任务、大信息量及实时高通速信的要求,具有较强的实用价值。     

Vision-based mobile robots on highways

Intelligent vehicles are mobile robots on highways. They are expected to improve the safety, efficiency and environmental impacts of the current highway traffic systems. Vision systems will play an important role as sensors for the intelligent vehicles. This paper first compares the vision sensors with other sensing methods from an application point of view and then describes two vision systems, one which we have developed and another which we are developing. Two important features are required for the vision systems applied to intelligent vehicles: three-dimensional (3D) measurement capability and real-time operation. We chose a trinocular stereo vision scheme among a number of 3D vision processing methods because it is suitable for real-time operations with dedicated processor architectures. The trinocular stereo algorithm requires a large number of operations, but all the operations are relatively straightforward and, therefore, they are suitable for custom architecture implementation. The system takes three images simultaneously by using three TV cameras installed on a single horizontal line at the front grill of the test car. Vertical edges are extracted from these images and the spatial offsets (or disparities) among the images are calculated for measuring the distances to the objects. The first version was developed and installed in a car for highway testing. Two custom digital processors were developed: one for edge detection and the other for stereo matching. The test results were encouraging and the architectures based on ASIC (Application Specific Integrated Circuits) are 800 and 550 times more efficient, respectively, compared with conventional microprocessors for edge detection and stereo matching. The second version is currently being developed in order to further reduce the silicon area size. It uses hybrid analog/digital circuit technology while the first version uses only digital circuits. We are developing a hybrid analog/digital array processor chip which includes a large number of processing elements. Each processing element includes a digital memory unit, a data flow control switch unit and an analog arithmetic/logic unit. The analog arithmetic/logic unit reduces the silicon area size significantly compared with the digital one. The data flows among multiple processing elements in the array chip in a form of analog voltage. The data flow is controlled by the data flow switches. The digital memory unit controls the set-up of the data flow control switch and arithmetic/logic units.     

云计算环境下分布式大数据多信道并行控制系统

分布式大数据控制受到信道数量影响易产生不同步现象,导致信道控制性能较差,设计一种云计算环境下分布式大数据多信道并行控制系统。系统硬件：节点处理模块由FPGA芯片以及抗干扰器组成;无线通信模块主要由射频芯片与无线收发器组成;USB模块由接口芯片、寄存器、存储芯片以及周边电路构成。系统软件：分布式大数据多信道数据存储与处理模块的构成为同步存储数据单元与数据多路实时处理单元;多信道并行控制模块主要由多信道并行管理单元、多信道状态扫查单元以及生成数据流单元构成。通过硬件与软件相结合实现了分布式大数据多信道并行控制。实验结果证明,分布式大数据信道平均传输速率数据则分布、保持的较为均匀,实现了性能提升。     

基于FPGA的链路层处理芯片S19202的配置

AMCC公司出品的链路层处理芯片S19202在实际应用中需要先进行硬件配置。通过在FPGA内部编程将其实现。本文介绍其实现方法,并给出了时序仿真波形和测试结果。     

一种新型微流体系统设计与合理性分析

微流体系统作为一种可对流体进行精密控制、操作与检测的技术,其发展为细胞体外培养提供了新的平台,而且可与生物传感器结合构成微流体传感测试系统,大大提高细胞传感检测的精确性、一致性和稳定性。在微系统设计与制造的基础上,提出了一种新型微流体系统结构,应用COMSOL软件建立了微流体系统模型,通过对其流动特性的分析对比,优化了系统结构,系统地研究了其对细胞培养与检测的影响。结果表明:该结构既能实现细胞的长期培养;又能通过精确的微流控制,结合生物传感器,对不同时期或不同病态的细胞进行实时检测和分析。该研究对医用药物测试芯片与微流传感测试系统有着重要的意义。     

基于MMX-VPU的Simatic控制系统的人工智能模块

Simatic控制系统对特定场景信息的识别能力较差,整体响应时间较长。为了完善系统功能,利用MMX-VPU设计了人工智能模块,该模块由识别单元和处理单元两部分组成,识别单元的核心设备为摄像机和加速度计,使用的芯片为型号为FM11RF08的非接触式识别芯片,处理单元在集成接口上安装了可兼容的传感器,使用的处理芯片名称为Tensor Processing Units,通过神经系统完成运行。通过WinAC提供的软件PLC和插槽PLC来实现人工智能模块硬件PLC的识别和处理功能。为检测人工智能模块工作效果,设定对比实验,结果表明,加入人工智能模块的Simatic控制系统识别效率更快,响应时间更短。     

Controlled counter-flow motion of magnetic bead chains rolling along microchannels

We demonstrate controlled transport of superparamagnetic beads in the opposite direction of a laminar flow. A permanent magnet assembles 200 nm magnetic particles into about 200 μm long bead chains that are aligned in parallel to the magnetic field lines. Due to a magnetic field gradient, the bead chains are attracted towards the wall of a microfluidic channel. A rotation of the permanent magnet results in a rotation of the bead chains in the opposite direction to the magnet. Due to friction on the surface, the bead chains roll along the channel wall, even in counter-flow direction, up to at a maximum counter-flow velocity of 8 mm s⁻¹. Based on this approach, magnetic beads can be accurately manoeuvred within microfluidic channels. This counter-flow motion can be efficiently be used in Lab-on-a-Chip systems, e.g. for implementing washing steps in DNA purification.     

An integrated flow-cell for full sample stream control

In this study, we present a novel three-dimensional hydrodynamic sheath flow chip that allows full control of a sample stream. The chip offers the possibility to steer each of the four side sheath flows individually. The design of the flow-cell exhibits high flexibility in creating different sample stream profiles (width and height) and allows navigation of the sample stream to every desired position inside the microchannel (vertical and horizontal). This can be used to bring the sample stream to a sensing area for analysis, or to an area of actuation (e.g. for cell sorting). In addition, we studied the creation of very small sample stream diameters. In microchannels (typically 25 × 40 μm2), we created sample stream diameters that were five to ten times smaller than the channel dimensions, and the smallest measured sample stream width was 1.5 μm. Typical flow rates are 0.5 μl/min for the sample flow and around 100 μl/min for the cumulated sheath flows. The planar microfabricated chip, consisting of a silicon–glass sandwich with an intermediate SU-8 layer, is much smaller (6 × 9 mm2) than the previously presented sheath flow devices, which makes it also cost-effective. We present the chip design, fluidic simulation results and experiments, where the size, shape and position of the sample stream have been established by laser scanning confocal microscopy and dye intensity analysis.     

Linux平台的卫星通信终端物理层控制软件设计

参考地球同步卫星移动通信接口标准GMR-13G,基于实现对基带芯片的资源调度以及基带芯片的射频一致性测试和协议一致性测试的目的,依据物理层过程设计了终端物理层控制软件.该软件综合考虑了基带芯片内各处理单元的动态行为和时序关系,采取脉冲中断和信号量机制驱动并控制基带芯片各个功能部件协同工作,配合卫星终端综测仪完成基带芯片的协议一致性测试以及终端联测,测试验证了该软件功能的正确性和有效性.     

A dielectrophoresis-based microdevice coated with nanostructured TiO2 for separation of particles and cells

In this study, we present a microdevice coated with titanium dioxide for cells and particles separation and handling. The microsystem consists of a pair of planar interdigitated gold micro-electrode arrays on a quartz substrate able to generate a traveling electric completed with a microfabricated three-dimensional glass structure for cell confinement. Dielectrophoretic forces were exploited for both vertical and lateral cell motions. In order to provide a biocompatible passivation layer to the electrodes a highly biocompatible nanostructured titanium dioxide film was deposited by supersonic cluster beam deposition (SCBD) on the electrode array. The dielectrophoretic effects of the chip were initially tested using polystyrene beads. To test the biocompatibility and capability of dielectrophoretic cell movement of the device, four cell lines (NIH3T3, SH-SY5Y, MDCK, and PC12) were used. Separation of beads from SH-SY5Y cells was also obtained.     

A single 1.5-V digital chip for a 106 synapse neuralnetwork

A digital-chip architecture for a 10(6)-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4-mmx18.6-mm chip by using a 0.5-mum CMOS design rule. A scaled-down version of the chip that has an 8-kb DRAM cell array was fabricated, and its operation was confirmed.     

A class of systolic multiplier units for VLSI technology

A high speed multiplier unit is an indispensable part of many applications such as real-time speech processing, image processing and enhancing, pattern classification, fast fourier transformation, etc. Because of its importance, the design of a fast multiplier unit has been under investigation since the 1950's. In addition, recent development in technology has motivated the design and implementation of fast multiplier units for VLSI technology. Some of these algorithms are still hard to implement due to their irregular structure with a high ratio of PINs per chip.This paper addresses a fast systolic multiplier unit suitable for VLSI technology. The system is a collection of two basic components replicated in a 2-dimensional space. Such a recursive structure offers simplicity in the design and implementation. Moreover, in comparison with the alternative models, the proposed pipeline architecture reduces the number of required ports (PINs) per chip by a factor of two.     

电力企业业扩报装冗余信息抽取系统设计

针对传统系统处理冗余信息工作频率低,冗余率高的问题,设计一个新的电力企业业扩报装冗余信息抽取系统。该系统采用B/S三层结构设计框架,框架主要由集成层、通信层以及抽取处理层组成,集成层主要由数据仓库集成芯片和通信接口组成,负责将电力企业业扩报装信息集中到一起;通信层中只有一个nRF2401芯片,负责将集成后的数据信息传输到抽取处理层中;抽取处理层主要由单片机和内外储存载体组成,主要负责抽取冗余信息,并将处理好的信息储存起来。结果表明:本系统较传统系统工作频率提高66.9 Hz,冗余率降低6.3%。     

新型气体涡街流量变送器设计

设计了一种新型气体涡街流量变送器以简化测量系统结构,改善测量性能。变送器由信号测量单元与信号处理单元组成,测量单元同时对漩涡频率、被测气体温度和压力进行检测,信号处理单元以单片机为核心,通过软件对流量测量信号进行温度、压力补偿和非线性修正等处理以减少测量误差。实验测试结果表明:变送器性能指标达到了设计要求。     

基于NIOSⅡ软核处理器的嵌入式测试系统软硬件设计研究

介绍了利用NIOSⅡ软核处理器设计嵌入式测试系统的两类系统架构,详细讲述了基于NIOSⅡ软核处理器的嵌入式测试系统软硬件设计方法;最后结合EP2C8Q-208C8型FPGA芯片,利用Verilog语言描述A/D芯片的工作时序逻辑,利用NIOSⅡ软核处理器设计串口处理单元,将A/D采集的数据通过串口发送到计算机显示。实践表明,利用NIOS II软核处理器设计嵌入式测试系统,具有开发周期短,系统集成度高,功能灵活多样等特点,与传统利用单片机设计嵌入式测试系统相比,具有时钟频率高、运行速度快、调试方便等特点,是一种值得推广的嵌入式测试系统设计方法。     

Performance tuning and sparse traversal technique for a cell‐based fetch length algorithm on a GPU

For determining distances (fetch lengths) from points to polygons in a two‐dimensional Euclidean plane, cell‐based algorithms provide a simple and effective solution. They divide the input area into a grid of cells that cover the area. The objects are stored into the appropriate cells, and the resulting structure is used for solving the problem. When the input objects are distributed unevenly or the cell size is small, most of the cells may be empty. The representation is then called sparse. In the method proposed in this work, each cell contains information about its distance to the nonempty cells. It is then possible to skip over several empty cells at a time without memory accesses. A cell‐based fetch length algorithm is implemented on a graphics processing unit (GPU). Because control flow divergence reduces its performance, several methods to reduce the divergence are studied. While many of the explicit attempts turn out to be unsuccessful, sorting of the input data and sparse traversal are observed to greatly improve performance: compared with the initial GPU implementation, up to 45‐fold speedup is reached. The speed improvement is greatest when the map is very sparse and the points are given in a random order. Copyright © 2015 John Wiley & Sons, Ltd.