A fourth-order /spl Sigma//spl Delta/ interface for micromachined inertial sensors

This paper presents the design and implementation of a high-order /spl Sigma//spl Delta/ interface for micromachined inertial sensors, which employs an electronic filter in series with the mechanical sensor element to reject the excessive in-band quantization noise inherently present in state-of-the-art second-order solutions. A fourth-order prototype was fabricated in a standard 0.5-/spl mu/m CMOS process. The active circuit area measures 0.9 mm/sup 2/, and the interface consumes 13 mW from a 5-V supply and achieves resolution of 1/spl deg//s//spl radic/Hz with a gyroscope and 150/spl mu/g//spl radic/Hz with an accelerometer. Comparison between the measured and simulated behavior of the system shows that the contribution of the quantization error to the total noise is negligible.     

Noise analysis and characterization of a sigma-delta capacitive microaccelerometer

This paper reports a high-sensitivity low-noise capacitive accelerometer system with one micro-g//spl radic/Hz resolution. The accelerometer and interface electronics together operate as a second-order electromechanical sigma-delta modulator. A detailed noise analysis of electromechanical sigma-delta capacitive accelerometers with a final goal of achieving sub-/spl mu/g resolution is also presented. The analysis and test results have shown that amplifier thermal and sensor charging reference voltage noises are dominant in open-loop mode of operation. For closed-loop mode of operation, mass-residual motion is the dominant noise source at low sampling frequencies. By increasing the sampling frequency, both open-loop and closed-loop overall noise can be reduced significantly. The interface circuit has more than 120 dB dynamic range and can resolve better than 10 aF. The complete module operates from a single 5-V supply and has a measured sensitivity of 960 mV/g with a noise floor of 1.08 /spl mu/g//spl radic/Hz in open-loop. This system can resolve better than 10 /spl mu/g//spl radic/Hz in closed-loop.     

An offset-canceling low-noise lock-in architecture for capacitive sensing

We describe an offset-canceling low-noise lock-in architecture for capacitive sensing. We take advantage of the properties of modulation and demodulation to separate the signal from the DC offset and use nonlinear multiplicative feedback to cancel the offset. The feedback also attenuates out-of-band noise and further enhances the power of a lock-in technique. Experimentally, in a 1.5-/spl mu/m BiCMOS chip, a fabrication DC offset of 2 mV and an intentional offset of 100 mV were attenuated to 9 /spl mu/V. Our offset-canceling technique could also be useful for practical multipliers that need tolerance to fabrication errors. We present a detailed theoretical noise analysis of our architecture that is confirmed by experiment. As an example application, we demonstrate the use of our architecture in a simple capacitive surface-microelectromechanical-system vibration sensor where the performance is limited by mechanical Brownian noise. However, we show that our electronics limits us to 30 /spl mu/g//spl radic/Hz, which is at least six times lower than the noise floor of commercial state-of-the-art surface-micromachined inertial sensors. Our architecture could, thus, be useful in high-performance inertial sensors with low mechanical noise. In a 1-100-Hz bandwidth, our electronic detection threshold corresponds to a one-part-per-eight-million change in capacitance.     

A CMOS chopper amplifier

A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.     

Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

Amplifier techniques for combining low noise, precision, and high-speed performance

A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

GaAs-based high-gain direct-coupled distributed preamplifier using active feedback topology

A single-chip ultra-high gain distributed amplifier (DA) was developed using commercial GaAs PHEMT foundry for 40-Gb/s base band applications. Two seven-section DAs are directly coupled using a lumped dc level-shift circuit. The dc bias level of the second-stage DA can be tuned using the level-shift circuit for optimum gain. The gain of each DA stage has been optimized using a novel active feedback cascode topology, which allows the gain bandwidth product to be maximized while avoiding instability problems. The fabricated single-chip DA with a size of 2.1 mm /spl times/ 2.3 mm showed a high gain of 28 dB, and an average noise figure of 4.6 dB with a 41 GHz bandwidth. The corresponding transimpedance gain was 62 dB/spl Omega/ and the input noise current density was 14.5 pA//spl radic/Hz. The gain bandwidth product (GBWP) is 1030 GHz, which corresponds to the highest performance using GaAs technology for 40 Gb/s applications.     

An inductance enhancement technique and its application to a shunt-peaked 2.5 Gb/s transimpedance amplifier design

This brief presents a bandwidth enhancement technique that is applicable to gigahertz-range broadband circuits. Using the inductance enhancement technique proposed in this brief, a 2.5-Gb/s transimpedance amplifier (TIA) has been implemented based on a 0.35-/spl mu/m CMOS technology. With the input noise reduction, the TIA with the proposed active inductor loads improves the overall system performances including more that 90% increase in bandwidth. Measurements show the bandwidth of 1.73 GHz, transimpedance gain of 68 dB/spl Omega/, and the averaged input referred noise current of 3.3 pA//spl radic/Hz, respectively, while dissipating 50 mW of dc power.     

RF HBT oscillators with low-phase noise and high-power performance utilizing a (/spl lambda//4/spl plusmn//spl delta/) open-stubs resonator

This paper presents a new type of transmission-line resonator and its application to RF (microwave and millimeter-wave) heterojunction bipolar transistor (HBT) oscillators. The resonator is a parallel combination of two open stubs having length of /spl lambda//4/spl plusmn//spl delta/(/spl delta//spl Lt//spl lambda/), where /spl lambda/ is a wavelength at a resonant frequency. The most important feature of this resonator is that the coupling coefficient (/spl beta//sub C/) can be controlled by changing /spl delta/ while maintaining unloaded Q-factor (Q/sub u/) constant. Choosing a small value of /spl delta/ allows us to reduce /spl beta//sub C/ or equivalently to increase loaded Q-factor (Q/sub L/). Since coupling elements such as capacitors or electromagnetic gaps are not needed, /spl beta//sub C/ and Q/sub L/ can be precisely controlled based on mature lithography technology. This feature of the resonator proves useful in reducing phase noise and also in enhancing output power of microwave oscillators. The proposed resonator is applied to 18-GHz and 38-GHz HBT oscillators, leading to the phase noise of -96-dBc/Hz at 100-kHz offset with 10.3-dBm output power (18-GHz oscillator) and -104-dBc/Hz at 1-MHz offset with 11.9 dBm (38-GHz oscillator). These performances are comparable to or better than state-of-the-art values for GaAs- or InP-based planar-circuit fundamental-frequency oscillators at the same frequency bands.     

CMOS wideband amplifiers using multiple inductive-series peaking technique

This work presents the technique of multiple inductive-series peaking to mitigate the deteriorated parasitic capacitance in CMOS technology. Employing multiple inductive-series peaking technique, a 10-Gb/s optical transimpedance amplifier (TIA) has been implemented in a 0.18-/spl mu/m CMOS process. The 10-Gb/s optical CMOS TIA, which accommodates a PD capacitor of 250 fF, achieves the gain of 61 dB/spl Omega/ and 3-dB frequency of 7.2 GHz. The noise measurement shows the average noise current of 8.2 pA//spl radic/Hz with power consumption of 70 mW.     

1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.     

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.     

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.     

Cryogenic capacitive transimpedance amplifier for astronomical infrared detectors

We have developed a new capacitive transimpedance amplifier (CTIA) that can be operated at 2 K, and have good performance as readout circuits of astronomical far-infrared array detectors. The circuit design of the present CTIA consists of silicon p-MOSFETs and other passive elements. The process is a standard Bi-CMOS process with 0.5 /spl mu/m design rule. The open-loop gain of the CTIA is more than 300, resulting in good integration performance. The output voltage swing of the CTIA was 270 mV. The power consumption for each CTIA is less than 10 /spl mu/W. The noise at the output showed a 1/f noise spectrum of 4 /spl mu/V//spl radic/Hz at 1 Hz. The performance of this CTIA nearly fulfills the requirements for the far-infrared array detectors onboard ASTRO-F, Japanese infrared astronomical satellite to be launched in 2005.     

An NMOS comparator for a bubble memory

A low-noise low-offset comparator was designed for a bubble memory system. The measured noise performance was 25 /spl mu/V rms or 13 nV//spl radic/Hz and the worst case offset voltage was determined to be 158 /spl mu/V. This results in a 1.30 mV comparator gray region.     

A compact 43-GHz monolithic differential VCO in 0.5-/spl mu/m InP DHBT technology

A compact monolithic integrated differential voltage controlled oscillator (VCO) using 0.5-/spl mu/m emitter width InP/InGaAs double-heterostructure bipolar transistors with a total chip size of 0.42 mm /spl times/ 0.46 mm is realized by using cross-coupled configuration for extremely high frequency satellite communications system applications. The device performance of F/sub max/ greater than 320 GHz at a current density of 5 mA//spl mu/m/sup 2/ and 5-V BVceo allows us to achieve a low phase noise 42.5-GHz fundamental VCO with -0.67-dBm output power. The VCO exhibits the phase noise of -106.8 dBc/Hz at 1-MHz offset and -122.3 dBc/Hz at 10-MHz offset from the carrier frequency.     

A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS

This paper presents a 0.18-/spl mu/m CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous-time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, -2 dBm out-of-band IIP3, -10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and -155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply.     

Millimeter-wave voltage-controlled oscillators in 0.13-/spl mu/m CMOS technology

This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.