用Verilog HDL进行FPGA设计的一些基本方法

随着FPGA技术和自动设计工具的进步．数字电子系统设计的方法正在发生变化。越来越多的工程师开始使用硬件描述语言和高级综合工具进行设计、Verilog HDL作为一种流行的硬件描述语言．在数字系统设计特别是FPGA设计中有着广泛的应用。本文主要介绍了用Verilog HDL进行FPGA设计和优化的一些实用方法．最后还介绍了IP核复用技术在FPGA设计中的应用。     

Enabling fuzzy technologies in high performance networking via an open FPGA-based development platform

Soft computing techniques and particularly fuzzy inference systems are gaining momentum as tools for network traffic modeling, analysis and control. Efficient hardware implementations of these techniques that can achieve real-time operation in high-speed networking equipment as well as other highly time-constrained application fields is however an open problem. We introduce a development platform for fuzzy inference systems with applications to network traffic analysis and control. The platform addresses the current requirements and constraints of high performance networking equipment. For the development process, we set up a methodology and a CAD tool chain that span the entire design process from initial specification in a high-level language to implementation on FPGA devices. An FPGA development board with PCI/PCIe interface is employed to support an open platform that comprises CAD tools as well as IP cores. PCI compatible fuzzy inference modules are implemented as System-on-Programmable-Chip (SoPC). We present satisfactory experimental results from the implementation of fuzzy systems for a number of applications in analysis and control of Internet traffic. These systems are shown to satisfy operational and architectural requirements of current and future high performance routing equipment. The platform proposed allows for the development of prototypes while avoiding large investments and complicated management procedures which constrain the testing and adoption of soft computing techniques in high performance networking.     

一种SOC原型机的建立与IP模块验证

SOC（System On Chip）将原来分立器件实现的CPUs、DSPs和存储器等模块整合在一个单芯片内,这种设计方法使得外围的IP模块的复用变得非常重要.而复用的IP模块必须嵌入到SOC中进行系统验证后才能使用,系统功能验证通常使用原型机的验证方法.该文论述了汉芯SOC的FPGA原型机验证环境的实现方法,以及如何使用串口建立起PC机与原型机的通讯.原型机验证中的一个普遍问题是ASIC设计代码不能直接映射到FPGA,否则会造成FPGA实现的硬件效率低,甚至时序不能满足从而导致验证失败,该文以门控时钟为例,对这种代码的转换提出一种可行的方法,并对转换前后的性能做了对比.最后,以一个常用的IP模块为例,对复用IP模块的系统原型机实时验证进行技术研究与探讨.     

基于FPGA的等精度频率计IP Core设计

介绍了等精度频率测量方法的原理及误差分析,利用基于FPGA的SoPC技术在QuartusⅡ5.0环境下用VHDL语言实现了等精度频率计的软核IPCore设计,并在相应的开发平台上作了验证。     

基于FPGA的千兆网络数据采集系统设计与实现

介绍了网络流量管理中的网络数据采集系统的设计与实现。以Altera StratixGX系列FPGA为平台,结合Marvell 88E1111网络芯片,完成了网络数据采集系统。本设计采用SoPC技术,利用Altera提供的千兆以太网IP核,完成FPGA系统无缝连接千兆以太网,实现网络数据包采集。     

基于Impulse—C的可重构编程技术研究

可重构计算的研究使用高度灵活的计算结构进行高性能计算。近年来采用FPGA器件来创建可重计算平台的研究大量出现。基于高级语言的FPGA编程技术可以让软件工程师摆脱硬件的干扰,致力于算法的实现。Impulse C语言工具集就是一种对软硬件划分和软硬件过程协同设计的相对简单的、基于C语言的方法,它与高效的基于FPGA的硬件编译器相结合,形成了一种完整的混合处理器和FPGA实现的方法。这些工具极大地简化了可重构部件的设计过程,但是在高效性和电路优化等方面跟手工设计仍有差距。     

A metaprogrammed C++ framework for hardware/software component integration and communication

With the ever growing complexity of System-on-Chip design, a considerable effort has been made to introduce higher levels of abstraction and to integrate high-level synthesis solutions to the design flow. In such design flows, a uniform communication interface is needed to enable high-level implementations of SoC components regardless of whether they are compiled as software running on a processor or synthesized to dedicated hardware IPs. This paper addresses this issue and proposes a component communication framework that defines an object-oriented remote call mechanism which allows transparent communication across hardware/software boundaries. The proposed framework relies on C++ static metaprogramming techniques to efficiently abstract communication between components implemented using high-level C++. We also define a portability layer that enables the migration of designs throughout different hardware platforms, operating systems, and tools. We assessed the performance and area footprint of our communication infrastructure through the implementation of a voice processing pipeline on top of a Network-on-Chip based architecture. Our results, when compared to previous related works with the same set of capabilities, show that our mechanisms yield small overhead in terms of software memory (up to 64% smaller), FPGA resources (up to 40% smaller), and hardware/software communication latency (up to 51% smaller).     

基于PLB总线的H.264整数变换量化软核的设计

提出了在FPGA上实现H.264中整数变换量化的方法,设计了基于动态数据宽度和流水线技术的软核(IP),在处理速度和硬件资源方面分别进行优化。此软核作为PowerPC的一个硬件加速模块在Xilinx Virtex-ⅡPRO中进行了验证。实验表明,在目前较难使用软件方法实现高分辨率图像实时编码的情况下,本文设计的软核能够提供2110MPixels/s的编码速率,完全适应实时编码。     

可进化芯片的FPGA接口设计与实现

针对FPGA IP核在可进化可编程系统芯片(SoPC)中嵌入时存在FPGA IP核端口时序控制和位流下载的问题,实现一种适用于可进化SoPC芯片的FPGA接口。该FPGA接口使用异步FIFO、双口RAM的结构和可扩展的读/写命令传输方式来实现FPGA IP核与系统的异步通信。嵌入式CPU可以通过FPGA接口实现FPGA IP核的片内位流配置。FPGA接口中的硬件随机数发生器实现进化算法的硬件加速。使用自动验证平台与FPGA原型验证平台对FPGA接口进行验证来实现验证的收敛。测试结果表明,FPGA接口成功实现了嵌入式CPU与FPGA IP核的通信,完成芯片内的进化。     

A dataflow approach to event-based debugging

This paper describes a novel approach to event-based debugging. The approach is based on a (coarsegrained) dataflow view of events: a high-level event is recognized when an appropriate combination of lower-level events on which it depends has occurred. Event recognition is controlled using familiar programming language constructs. This approach is more flexible and powerful than current ones. It allows arbitrary debugger language commands to be executed when attempting to form higher-level events. It also allows users to specify event recognition in much the same way that they write programs. This paper also describes a prototype, Dalek, that employs the dataflow approach for debugging sequential programs. Dalek demonstrates the feasibility and attractiveness of the dataflow approach. One important motivation for this work is that current sequential debugging tools are inadequate. Dalek contributes toward remedying such inadequacies by providing events and a powerful debugging language. Generalizing the dataflow approach so that it can aid in the debugging of concurrent programs is under investigation.     

线路保护装置SV直采传输方案研究

分析了当前智能变电站SV点对点发送处理机制,提出了一种满足过程层要求的高均匀性和一致性SV直采传输方法。应用FPGA实现DMA控制器和以太网MAC控制单元,对SV报文添加发送描述符,由FPGA根据描述符直接控制SV发送。采用Spartan-6系列架构FPGA,通过PCI Express总线,系统内部实现SV数据高速传输。此方案充分利用了FPGA的并行数据处理的特性及丰富的IP资源,设计实现了多路以太网点对点数据的高带宽和高可靠性传输,极大的提升了智能变电站系统的性能。     

基于PCIE点对点传输的FPGA系统

本文分析了当前智能变电站系统点对点数据传输互联并行总线的局限性,提出采用PCI Express高速串行接口技术,应用Spartan-6 XC6SLX45T架构FPGA,实现点对点以太网数据传输的设计方案. 此方案充分利用了FPGA的并行数据处理的特性及丰富的IP资源,设计实现了多路以太网点对点数据的高带宽和高可靠性传输,极大的提升了智能变电站系统的性能.     

Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system

The DEFACTO compilation and synthesis system is capable of automatically mapping computations expressed in high-level imperative programming languages as C to FPGA-based systems. DEFACTO combines parallelizing compiler technology with behavioral VHDI, synthesis tools to guide the application of high-level compiler transformations in the search of high-quality hardware designs. In this article we illustrate the effectiveness of this approach in automatically mapping several kernel codes to an FPGA quickly and correctly. We also present a detailed example of the comparison of the performance of an automatically generated design against a manually generated implementation of the same computation. The design-space-exploration component of DEFACTO is able to explore a large number of designs for a particular computation that would otherwise be impractical for any designers.     

Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs

This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and tree-based lookahead architectures. Intrusion detection for network security is a compute-intensive application demanding high system performance. The tools implement and automate a customizable flow for the creation of efficient field programmable gate array (FPGA) architectures using system-level optimizations. Our methodology allows for customized performance through more efficient communication and extensive reuse of hardware components for dramatic increases in area-time performance     

Automating the design of SOCs using cores

Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks     

有功电能计量IP核的设计

对有功电能计量的数学模型进行了分析,给出了相应的IP核实现模型,并详细讨论了CIC抽取滤波器、IIR高通滤波器、FIR低通滤波器、数字频率变换等模块的原理与设计。利用Simulink模型进行了仿真,用VHDL作为设计语言,在QuartusⅡ软件下完成综合和仿真,并在Altera公司的FPGA芯片CycloneⅡEP2C35F484C8目标板上实现设计。     

FPGA-based implementation of a chirp signal generator using an OpenCL design

A novel approach to developing an FPGA-based chirp signal generator using high-level synthesis implementation is proposed. OpenCL, which is a framework used for high-level synthesis (HLS) methodologies, is employed instead of the Verilog/VHDL language to program FPGA. OpenCL has been used for FPGA programming, particularly in high-performance computing applications. Utilizing OpenCL for FPGA development reduces development time because of the high-level abstraction of the code. However, compared to Verilog/VHDL, standard OpenCL does not enable direct access to the FPGA's I/O. In this study, the FPGA needs to access the I/O pins to communicate with the DAC and generate the chirp signal. Thus, direct access to the FPGA I/O pin from the OpenCL environment is required. Therefore, a new OpenCL component is developed to enable the FPGA to communicate with the DAC, thus allowing data streaming to generate the chirp signal. This OpenCL component enables us to stream the data from the FPGA to generate the chirp signal. Here, we demonstrate that by using OpenCL implementation, the FPGA can generate an I/Q chirp signal efficiently. Moreover, the same OpenCL kernel can be employed to generate different bandwidths of the chirp signal without having to reprogram the FPGA. To demonstrate the capability of the system, we generated the I/Q chirp signal from 1 MHz to 5 MHz, 5 MHz to 10 MHz, 10 MHz to 15 MHz and 15 MHz to 20 MHz for a period of 10 µs.     

High-level debugging of distributed systems: The behavioral abstraction approach

Most extant debugging aids force their users to think about errors in programs from a low-level, unit-at-a-time perspective. Such a perspective is inadequate for debugging large complex systems, particularly distributed systems. In this paper, we present a high-level approach to debugging that offers an alternative to the traditional techniques. We describe a language, edl, developed to support this high-level approach to debugging and outline a set of tools that has been constructed to effect this approach. The paper includes an example illustrating the approach and discusses a number of problems encountered while developing these debugging tools.