Novel Design of a 2.5-GHz Fully Integrated CMOS Butler Matrix for Smart-Antenna Systems

This paper presents a novel design of monolithic 2.5-GHz 4 $,times,$4 Butler matrix in 0.18- $mu$m CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Butler matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of ${hbox{45}}{pm}{hbox{3}}^{circ}, ~{hbox{135}} pm {hbox{4}}^{circ}, ~ -{hbox{45}} pm {hbox{3}}^{circ}, ~{hbox{and}}~ -{hbox{135}} pm {hbox{4}}^{circ}$ with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1$,times,$ 4 monopole antenna array. The generated beams are pointing to $-{hbox{45}}^{circ}, ~ -{hbox{15}}^{circ}$ , 15$^{circ}$, and 45$^{circ}$, respectively, with less than 1$^{circ}$ error, which agree very well with the predictions. This Butler matrix consumes no dc power and only occupies the chip area of 1.36 $,times,$1.47 mm$^{2}$ . To our knowledge, this is the first demonstration of the single-chip Butler matrix in CMOS technology.      

On Parallelepiped-Shaped Passbands for Multidimensional Nonseparable ${bf M}$th-Band Low-Pass Filters

The “shape” of the desired frequency passband is an important consideration in the design of nonseparable multidimensional ($M$ -D) filters in $M$-D multirate systems. For $M$-D ${bf M}$th-band filters, the passband shape should be chosen such that the ${bf M}$th-band constraint is satisfied. The most commonly used shape of the passband for $M$-D ${bf M}$ th-band low-pass filters is the so-called symmetric parallelepiped (SPD) ${rm SPD}(pi {bf M}^{- {rm T}})$ . In this paper, we consider the more general parallelepiped passband ${rm SPD}(pi {bf L} ^{rm T})$, and derive conditions on $ {bf L} $ such that the ${bf M}$ th-band constraint is satisfied. This result gives some flexibility in designing $M$-D ${bf M}$th-band filters with parallelepiped shapes other than the commonly used case of $ {bf L} = {bf M}^{- 1}$. We present design examples of 2-D ${bf M}$th-band filters to illustrate this flexibility in the choice of $ {bf L} $.      

Fast joint reconstruction of dynamic R2* and field maps in functional MRI

Blood oxygen level dependent (BOLD) functional magnetic resonance imaging (fMRI) is conventionally done by reconstructing ${T}_{2}^{*}$-weighted images. However, since the images are unitless they are nonquantifiable in terms of important physiological parameters. An alternative approach is to reconstruct ${R}_{2}^{*}$ maps which are quantifiable and have comparable BOLD contrast as ${T}_{2}^{*}$-weighted images. However, conventional ${R}_{2}^{*}$ mapping involves long readouts and ignores relaxation during readout. Another problem with fMRI imaging is temporal drift/fluctuations in off-resonance. Conventionally, a field map is collected at the start of the fMRI study to correct for off-resonance, ignoring any temporal changes. Here, we propose a new fast regularized iterative algorithm that jointly reconstructs ${R}_{2}^{*}$ and field maps for all time frames in fMRI data. To accelerate the algorithm we linearize the MR signal model, enabling the use of fast regularized iterative reconstruction methods. The regularizer was designed to account for the different resolution properties of both ${R}_{2}^{*}$ and field maps and provide uniform spatial resolution. For fMRI data with the same temporal frame rate as data collected for ${T}_{2}^{*}$-weighted imaging the resulting ${R}_{2}^{*}$ maps performed comparably to ${T}_{2}^{*}$-weighted images in activation detection while also correcting for spatially global and local temporal changes in off-resonance.      

A Hybrid Electrooptic Microring Resonator-Based $1 times 4times 1$ ROADM for Wafer Scale Optical Interconnects

Pairing high-quality factor $(Q)$ silicon-on-insulator microring resonators with rapidly tunable organic electrooptic claddings has allowed the first demonstration of a silicon-organic hybrid electrooptic reconfigurable optical add/drop multiplexer (ROADM). A coplanar electrode geometry provides up to 0.36 GHz/V of electrooptic voltage tuning for each channel, corresponding to an electrooptic coefficient of $r_{33}=64 hbox{pm/V}$ at wavelengths around 1550 nm. Individual ring resonator devices have 40- $mu{hbox {m}}$ ring radii, 2.7-nm free spectral range, and tuning ranges of 180 GHz. The $1times 4times 1$ ROADM has a footprint of less than 1 ${hbox {mm}}^{2}$ and has been shown to reconfigure in less than a microsecond.      

Active Matrix OTFT Display With Anodized Gate Dielectric

A complete process for an active-matrix (AM) organic thin-film transistor (OTFT) polymer dispersed liquid crystal (PDLC) display is presented. Evaporated pentacene is used as semiconductor. The display comprises 64$times$64 pixel, each with a pixel pitch of $({hbox{312.5}} times {hbox{312.5}}) mu{hbox{m}}^2$. The AM display is fabricated with standard photolithographic processes. Since all process temperatures are below 180$^{circ}$C the processes for the AM backplane can be easily transferred to plastic substrates like PEN or PET. Due to the thin anodically oxidized ${hbox{Al}}_2$ ${hbox{O}}_3$ gate dielectric with a thickness of 60 nm and $varepsilon_{rm r}=9$, driving voltages between 10 and 12 V are sufficient. To protect the pentacene against the PDLC, it is encapsulated with sputtered ${hbox{Ta}}_2 {hbox{O}}_5$ layer. After the passivation a field effect mobility of 0.2 ${hbox{cm}}^{2}/{hbox{V}}cdot{hbox{s}}$ is obtained for the OTFTs.      

Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of $2 ^{7} -1$, $2 ^{10} -1$, $2 ^{15} -1$, $2 ^{23} -1$, and $2 ^{31} -1~hbox{b}$ according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 ${hbox {ps}}_{rm rms}$, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-$mu{hbox {m}}$ CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.      

A 16-bit 65-MS/s Pipeline ADC With 80-dBFS SNR Using Analog Auto-Calibration in SiGe SOI Complementary BiCMOS

A 16-bit 65-MS/s switched-capacitors pipeline analog-to-digital converter built in 0.45-$mu{hbox {m}}$ 25-GHz $f_{T}$ complementary silicon-on-insulator BiCMOS delivers 80.1-dBFS signal-to-noise ratio, 98-dBc spurious-free dynamic range (SFDR) with 3-Vpp input range at 2-MHz input frequency. The $5times 5.3 {hbox {mm}}^{2}$ die consumes 1.7 W from a dual $pm$ 2.7-V supply. A noniterative analog auto-calibration algorithm simultaneously compensates for both random mismatch in the capacitors of the first quantizer stages, and integral nonlinearity curvatures contributed by sample-and-hold (S/H) and voltage reference buffers, yielding SFDR optimizations up to 12 dB. The test chip performance validates the transient noise simulations run for the analog front-end and the clock jitter, corroborating the efficacy of the circuit techniques adopted to design S/H, clock and references.      

Effect of Top Electrode Material on Resistive Switching Properties of ZrO2 Film Memory Devices

The influence of top electrode material on the resistive switching properties of $hbox{ZrO}_{2}$-based memory film using Pt as a bottom electrode was investigated in this letter. In comparison with $hbox{Pt/ZrO}_{2}/hbox{Pt}$ and $hbox{Al/ZrO}_{2}/hbox{Pt}$ devices, the $hbox{Ti/ZrO}_{2}/hbox{Pt}$ device exhibits different resistive switching current–voltage $(I$– $V)$ curve, which can be traced and reproduced by a dc voltage more than 1000 times only showing a little decrease of resistance ratio between high and low resistance states. Furthermore, the broad dispersions of resistive switching characteristics in the $hbox{Pt/ZrO}_{2}/hbox{Pt}$ and $hbox{Al/ZrO}_{2}/hbox{Pt}$ devices are generally observed during successive resistive switching, but those dispersions are suppressed by the device using Ti as a top electrode. The reliability results, such as cycling endurance and continuous readout test, are also presented. The write-read-erase-read operations can be over $hbox{10}^{4}$ cycles without degradation. No data loss is found upon successive readout after performing various endurance cycles.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific on -state resistance $(R_{{rm SP}hbox{-}{rm ON}})$ is as low as 3.0 $hbox{m}Omegacdothbox{cm}^{2}$, and the open-base breakdown voltage $(V_{rm CEO})$ reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 $times$ 4.1 mm have been successfully packaged into a high-gain $(beta = hbox{50.8})$ high-power (80 A $times$ 700 V) all-SiC copack and evaluated at high temperature up to 250 $^{circ}hbox{C}$. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 $hbox{A}/hbox{cm}^{2}$ for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

Endurance Reliability of Multilevel-Cell Flash Memory Using a $ hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ Dual Charge Storage Layer

The mechanisms of programming/erasing (P/E) and endurance degradation have been investigated for multilevel-cell (MLC) Flash memories using a $hbox{Si}_{3}hbox{N}_{4}$ (NROM) or a $hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ dual charge storage layer (DCSL). Threshold-voltage $(V_{rm th})$ -level disturbance is found to be the major endurance degradation factor of NROM-type MLCs, whereas separated charge storage and step-up potential wells give rise to a superior $V_{rm th}$ -level controllability for DCSL MLCs. The programmed $V_{rm th}$ levels of DCSL MLCs are controlled by the spatial charge distribution, as well as the charge storage capacity of each storage layer, rather than the charge injection. As a result, DCSL MLCs show negligible $V_{rm th}$-level offsets ($ ≪ $ 0.2 V) that are maintained throughout the $hbox{10}^{5}$ P/E cycles, demonstrating significantly improved endurance reliability compared to NROM-type MLCs.      

Current density impedance imaging

Current density impedance imaging (CDII) is a new impedance imaging technique that can noninvasively measure the conductivity distribution inside a medium. It utilizes current density vector measurements which can be made using a magnetic resonance imager (MRI) (Scott , 1991). CDII is based on a simple mathematical expression for $nablasigma/sigma=nablalnsigma$, the gradient of the logarithm of the conductivity $sigma$ , at each point in a region where two current density vectors ${bf J}_{1}$ and ${bf J}_{2}$ have been measured and ${bf J}_{1}times{bf J}_{2}neq 0$. From the calculated $nablalnsigma$ and a priori knowledge of the conductivity at the boundary, the logarithm of the conductivity $lnsigma$ is integrated by two different methods to produce an image of the conductivity $sigma$ in the region of interest. The CDII technique was tested on three different conductivity phantoms. Much emphasis has been placed on the experimental validation of CDII results against direct bench measurements by commercial LCR meters before and after CDII was performed.      

A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

A fully integrated CMOS frequency synthesizer for UHF RFID reader is implemented in a 0.18-$mu$m CMOS technology. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer's phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. The modified transformer feedback voltage-controlled oscillator (VCO) exhibits enhanced tank impedance and even harmonic noise filtering to achieve low phase noise. A third-order 2-bit single-loop $Sigma Delta$ modulator is optimized for the proposed synthesizer in terms of phase noise and power. The synthesizer provides a frequency resolution of 25-kHz with a tuning range from 1.03 GHz to 1.4 GHz . Phase noise of ${-}$70 dBc/Hz inband, ${-}$104 dBc/Hz at 200-kHz offset and ${-}$ 121 dBc/Hz at 1-MHz offset with a reference spur of ${-}$84 dBc are measured at a center frequency of 1.17 GHz and a loop bandwidth of 35 kHz. Power dissipation is 4.92 mW from a 0.8 V supply.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

Fabrication and Characterization of Temperature Insensitive 660-nm Resonant-Cavity LEDs

InGaP/AlGaInP 660-nm resonant-cavity light-emitting diodes (RCLEDs) with stable temperature characteristics have been achieved by extending the resonant cavity length from one optical wavelength $(1lambda)$ to three optical wavelengths $(3lambda)$ and tripling the number of quantum wells. When the operation temperature increases from 25 $^{circ}$C to 95 $^{circ}$ C, the degree of power variation at 20 mA is reduced from ${-}$2.1 dB to ${-}$0.6 dB for the conventional 1- $lambda$ cavity RCLEDs and 3- $lambda$ cavity RCLEDs, respectively. In order to interpret the temperature-dependent experimental results, advanced device simulation is applied to model the RCLEDs with different cavity designs. According to the numerical simulation results, we deduce that the stable temperature-dependent output performance should originate from the reduction of electron leakage current and thermally enhanced hole transport for the 3- $lambda$ cavity AlGaInP RCLEDs.      

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp

A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable- $g_{m}$ opamp. The ADC is implemented in 0.18 $muhbox{m}$ CMOS technology and occupies a die area of 0.86 ${hbox{mm}}^{2}$. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, ${-}$66.2 $~$dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

RF Power Measurements of InAlN/GaN Unstrained HEMTs on SiC Substrates at 10 GHz

Unstrained high-electron mobility transistors (HEMTs) were fabricated from InAlN/GaN on semi-insulating SiC substrates. The devices had 0.24-$muhbox{m}$ T-gates with a total width of $hbox{2} times hbox{150} muhbox{m}$. Final passivated performance values for these devices are $I_{max} = hbox{1279} hbox{mA/mm}$, $I_{rm DSS} = hbox{1182} hbox{mA/mm}$ , $R_{c} = hbox{0.43} Omega cdot hbox{mm}$, $rho_{s} = hbox{315} Omega/hbox{sq}$, $f_{T} = hbox{45} hbox{GHz}$, $f_{max({rm MAG})} = hbox{64} hbox{GHz}$, and $g_{m} = hbox{268} hbox{mS/mm}$. Continuous-wave power measurements at 10 GHz produced $P_{rm sat} = hbox{3.8} hbox{W/mm}$, $G_{t} = hbox{8.6} hbox{dB}$, and $hbox{PAE} = hbox{30}%$ at $V_{rm DS} = hbox{20} hbox{V}$ at 25% $I_{rm DSS}$ . To our knowledge, these are the first power measurements reported at 10 GHz for this material.      

A 2–40 GHz Active Balun Using 0.13 $mu{rm m}$ CMOS Process

A 2 to 40 GHz broadband active balun using 0.13 $mu{rm m}$ CMOS technology is presented in this letter. Using two-stage differential amplified pairs, the active balun can achieve a wideband performance with the gain compensation technique. This active balun exhibits a measured small signal gain of ${0} pm{1}~{rm dB}$, with the amplitude imbalances below 0.5 dB and the phase differences of ${180} pm {10} ^{circ}$ from 2 to 40 GHz. The core active balun has a low power consumption of 40 mW, and a compact area of 0.8 mm $times,$ 0.7 mm. This proposed balun achieved the highest operation frequency, the widest bandwidth, and the smallest size among all the reported active baluns.